riscv/rocket-chip
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writebacks on release network pass asm tests and bmarks

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This commit is contained in:
Henry Cook
2013-02-28 18:11:40 -08:00
parent f5729c9f25
commit e0361840bd
4 changed files with 120 additions and 63 deletions
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5
rocket/src/main/scala/icache.scala
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@ -172,7 +172,8 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
val s2_miss = s2_valid && !s2_any_tag_hit
rdy := state === s_ready && !s2_miss
val (rf_cnt, refill_done) = Counter(io.mem.grant.valid, REFILL_CYCLES)
Assert(!c.co.isVoluntary(io.mem.grant.bits.payload) || !io.mem.grant.valid, "UncachedRequestors shouldn't get voluntary grants.")
val (rf_cnt, refill_done) = Counter(io.mem.grant.valid && !c.co.isVoluntary(io.mem.grant.bits.payload), REFILL_CYCLES)
val repl_way = if (c.dm) UFix(0) else LFSR16(s2_miss)(log2Up(c.assoc)-1,0)
val enc_tagbits = c.code.width(c.tagbits)
@ -223,7 +224,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
for (i <- 0 until c.assoc) {
val data_array = Mem(c.sets*REFILL_CYCLES, seqRead = true){ Bits(width = c.code.width(c.databits)) }
val s1_dout = Reg(){ Bits() }
when (io.mem.grant.valid && repl_way === UFix(i)) {
when (io.mem.grant.valid && c.co.messageHasData(io.mem.grant.bits.payload) && repl_way === UFix(i)) {
val d = io.mem.grant.bits.payload.data
data_array(Cat(s2_idx,rf_cnt)) := c.code.encode(d)
}