riscv/rocket-chip
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Don't implicitly fence on CSR instructions

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CSRs that have an effect on I/O should use an explicit FENCE.
This commit is contained in:
Andrew Waterman 2016-10-01 19:39:36 -07:00
parent b772edcb1b
commit e0188f8aa4
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/rocket.scala
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@ -263,7 +263,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc) mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)
id_reg_fence := id_fence_next || id_reg_fence && id_mem_busy id_reg_fence := id_fence_next || id_reg_fence && id_mem_busy
val id_do_fence = id_rocc_busy && id_ctrl.fence || val id_do_fence = id_rocc_busy && id_ctrl.fence ||
id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc) || id_csr_en) id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc))
val bpu = Module(new BreakpointUnit(nBreakpoints)) val bpu = Module(new BreakpointUnit(nBreakpoints))
bpu.io.status := csr.io.status bpu.io.status := csr.io.status