From e0188f8aa40f42d1e06ab0bb5ed57f5c1975eeea Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sat, 1 Oct 2016 19:39:36 -0700 Subject: [PATCH] Don't implicitly fence on CSR instructions CSRs that have an effect on I/O should use an explicit FENCE. --- src/main/scala/rocket/rocket.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/rocket.scala b/src/main/scala/rocket/rocket.scala index 404ed6a0..b71924d3 100644 --- a/src/main/scala/rocket/rocket.scala +++ b/src/main/scala/rocket/rocket.scala @@ -263,7 +263,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) { mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc) id_reg_fence := id_fence_next || id_reg_fence && id_mem_busy val id_do_fence = id_rocc_busy && id_ctrl.fence || - id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc) || id_csr_en) + id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc)) val bpu = Module(new BreakpointUnit(nBreakpoints)) bpu.io.status := csr.io.status