Better foldR
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@ -18,41 +18,43 @@ class MemData extends Bundle {
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}
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}
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class TransactionInit extends Bundle {
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class TransactionInit extends Bundle {
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val ttype = Bits(width = TTYPE_BITS)
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val t_type = Bits(width = TTYPE_BITS)
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val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
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val has_data = Bool()
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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val address = Bits(width = PADDR_BITS)
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}
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}
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class TransactionInitData extends MemData
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class TransactionInitData extends MemData
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class TransactionAbort extends Bundle {
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class TransactionAbort extends Bundle {
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val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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}
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}
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class ProbeRequest extends Bundle {
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class ProbeRequest extends Bundle {
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val ptype = Bits(width = PTYPE_BITS)
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val p_type = Bits(width = PTYPE_BITS)
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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val address = Bits(width = PADDR_BITS)
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}
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}
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class ProbeReply extends Bundle {
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class ProbeReply extends Bundle {
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val ptype = Bits(width = PTYPE_BITS)
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val p_type = Bits(width = PTYPE_BITS)
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val hasData = Bool()
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val has_data = Bool()
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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}
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class ProbeReplyData extends MemData
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class ProbeReplyData extends MemData
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class TransactionReply extends Bundle {
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class TransactionReply extends Bundle {
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val ttype = Bits(width = TTYPE_BITS)
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val t_type = Bits(width = TTYPE_BITS)
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val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
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val has_data = Bool()
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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}
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class TransactionReplyData extends MemData
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class TransactionReplyData extends MemData
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class TransactionFinish extends Bundle {
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class TransactionFinish extends Bundle {
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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}
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class ioTileLink extends Bundle {
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class ioTileLink extends Bundle {
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@ -142,7 +144,7 @@ trait FourStateCoherence extends CoherencePolicy {
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def getMetaUpdateOnProbe (incoming: ProbeRequest): Bits = {
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def getMetaUpdateOnProbe (incoming: ProbeRequest): Bits = {
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val state = UFix(0)
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val state = UFix(0)
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switch(incoming.ptype) {
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switch(incoming.p_type) {
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is(probeInvalidate) { state := tileInvalid }
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is(probeInvalidate) { state := tileInvalid }
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is(probeDowngrade) { state := tileShared }
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is(probeDowngrade) { state := tileShared }
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}
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}
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