273 lines
9.6 KiB
Scala
273 lines
9.6 KiB
Scala
package Top {
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import Chisel._
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import Constants._
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import hwacha.GenArray
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class HubMemReq extends Bundle {
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val rw = Bool()
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val addr = UFix(width = PADDR_BITS-OFFSET_BITS)
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val tag = Bits(width = GLOBAL_XACT_ID_BITS)
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// Figure out which data-in port to pull from
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val data_idx = Bits(width = TILE_ID_BITS)
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val is_probe_rep = Bool()
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}
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class MemData extends Bundle {
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val data = Bits(width = MEM_DATA_BITS)
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}
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class TransactionInit extends Bundle {
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val t_type = Bits(width = TTYPE_BITS)
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val has_data = Bool()
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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}
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class TransactionInitData extends MemData
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class TransactionAbort extends Bundle {
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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}
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class ProbeRequest extends Bundle {
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val p_type = Bits(width = PTYPE_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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}
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class ProbeReply extends Bundle {
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val p_type = Bits(width = PTYPE_BITS)
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val has_data = Bool()
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class ProbeReplyData extends MemData
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class TransactionReply extends Bundle {
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val t_type = Bits(width = TTYPE_BITS)
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val has_data = Bool()
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class TransactionReplyData extends MemData
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class TransactionFinish extends Bundle {
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class ioTileLink extends Bundle {
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val xact_init = (new ioDecoupled) { new TransactionInit() }.flip
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val xact_init_data = (new ioDecoupled) { new TransactionInitData() }.flip
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val xact_abort = (new ioDecoupled) { new TransactionAbort() }
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val probe_req = (new ioDecoupled) { new ProbeRequest() }
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val probe_rep = (new ioDecoupled) { new ProbeReply() }.flip
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val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() }.flip
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val xact_rep = (new ioDecoupled) { new TransactionReply() }
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val xact_rep_data = (new ioDecoupled) { new TransactionReplyData() }
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val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip
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}
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trait CoherencePolicy {
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def cpuCmdToRW( cmd: Bits): (Bool, Bool) = {
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val store = (cmd === M_XWR)
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val load = (cmd === M_XRD)
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val amo = cmd(3).toBool
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val read = load || amo || (cmd === M_PFR)
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val write = store || amo || (cmd === M_PFW)
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(read, write)
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}
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}
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trait ThreeStateIncoherence extends CoherencePolicy {
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val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
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def isHit ( cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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( state === tileClean || state === tileDirty)
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}
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def isValid (state: UFix): Bool = {
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state != tileInvalid
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}
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def needsWriteback (state: UFix): Bool = {
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state === tileDirty
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}
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def newStateOnWriteback() = tileInvalid
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def newStateOnFlush() = tileInvalid
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def newState(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileDirty, Mux(read, Mux(state === tileDirty, tileDirty, tileClean), state))
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}
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def newStateOnHit(cmd: Bits, state: UFix): UFix = newState(cmd, state)
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def newStateOnPrimaryMiss(cmd: Bits): UFix = newState(cmd, tileInvalid)
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def newStateOnSecondaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileDirty, state)
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}
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}
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trait FourStateCoherence extends CoherencePolicy {
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val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(4){ UFix() }
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val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() }
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val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() }
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def isHit ( cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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((read && ( state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty)) ||
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(write && (state === tileExclusiveClean || state === tileExclusiveDirty)))
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}
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def isValid (state: UFix): Bool = {
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state != tileInvalid
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}
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def needsWriteback (state: UFix): Bool = {
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state === tileExclusiveDirty
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}
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def newStateOnWriteback() = tileInvalid
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def newStateOnFlush() = tileInvalid
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// TODO: New funcs as compared to incoherent protocol:
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def newState(cmd: Bits, state: UFix): UFix
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def newStateOnHit(cmd: Bits, state: UFix): UFix
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def newStateOnPrimaryMiss(cmd: Bits): UFix
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def newStateOnSecondaryMiss(cmd: Bits, state: UFix): UFix
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def needsSecondaryXact (cmd: Bits, outstanding: TransactionInit): Bool
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def getMetaUpdateOnProbe (incoming: ProbeRequest): Bits = {
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val state = UFix(0)
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switch(incoming.p_type) {
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is(probeInvalidate) { state := tileInvalid }
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is(probeDowngrade) { state := tileShared }
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}
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state.toBits
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}
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}
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class XactTracker(id: Int) extends Component {
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val io = new Bundle {
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val xact_init = (new ioDecoupled) { new TransactionInit() }
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val probe_rep = (new ioDecoupled) { new ProbeReply() }
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val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip
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val xact_rep = (new ioDecoupled) { new TransactionReply() }.flip
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val mem_req = (new ioDecoupled) { new MemReq() }.flip
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val xact_finish = Bool(INPUT)
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val busy = Bool(OUTPUT)
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val addr = Bits(PADDR_BITS, OUTPUT)
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val tile_id = Bits(TILE_ID_BITS, OUTPUT)
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val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT)
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val sharer_count = Bits(TILE_ID_BITS, OUTPUT)
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val ttype = Bits(TTYPE_BITS, OUTPUT)
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}
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val valid = Reg(resetVal = Bool(false))
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val addr = Reg{ Bits() }
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val ttype = Reg{ Bits() }
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val tile_id = Reg{ Bits() }
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val tile_xact_id = Reg{ Bits() }
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val probe_done = Reg{ Bits() }
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}
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abstract class CoherenceHub extends Component
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class CoherenceHubNoDir extends CoherenceHub {
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def coherenceConflict(addr1: Bits, addr2: Bits): Bool = {
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addr1(PADDR_BITS-1, OFFSET_BITS) === addr2(PADDR_BITS-1, OFFSET_BITS)
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}
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def getTransactionReplyType(ttype: UFix, count: UFix): Bits = {
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val ret = Wire() { Bits(width = TTYPE_BITS) }
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switch (ttype) {
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is(X_READ_SHARED) { ret := Mux(count > UFix(0), X_READ_SHARED, X_READ_EXCLUSIVE) }
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is(X_READ_EXCLUSIVE) { ret := X_READ_EXCLUSIVE }
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is(X_READ_UNCACHED) { ret := X_READ_UNCACHED }
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is(X_WRITE_UNCACHED) { ret := X_WRITE_UNCACHED }
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}
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ret
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}
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val io = new Bundle {
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val tiles = Vec(NTILES) { new ioTileLink() }
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val mem = new ioDCache().flip
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}
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
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val busy_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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val addr_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS)} }
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val tile_id_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val tile_xact_id_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} }
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val sh_count_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val ttype_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TTYPE_BITS)} }
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val free_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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for( i <- 0 until NGLOBAL_XACTS) {
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busy_arr.write( UFix(i), trackerList(i).io.busy)
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addr_arr.write( UFix(i), trackerList(i).io.addr)
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tile_id_arr.write( UFix(i), trackerList(i).io.tile_id)
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tile_xact_id_arr.write(UFix(i), trackerList(i).io.tile_xact_id)
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ttype_arr.write( UFix(i), trackerList(i).io.ttype)
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sh_count_arr.write( UFix(i), trackerList(i).io.sharer_count)
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trackerList(i).io.xact_finish := free_arr.read(UFix(i))
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}
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// Nack conflicting transaction init attempts
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val aborting = Wire() { Bits(width = NTILES) }
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val initiating = Wire() { Bits(width = NTILES) }
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for( j <- 0 until NTILES ) {
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val init = io.tiles(j).xact_init
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val abort = io.tiles(j).xact_abort
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val conflicts = Bits(width = NGLOBAL_XACTS)
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for( i <- 0 until NGLOBAL_XACTS) {
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val t = trackerList(i).io
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conflicts(i) := t.busy(i) && coherenceConflict(t.addr, init.bits.address)
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}
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aborting(j) := (conflicts.orR || busy_arr.flatten().andR)
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abort.valid := init.valid && aborting
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abort.bits.tileTransactionID := init.bits.tileTransactionID
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init.ready := aborting(j) || initiating(j)
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}
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// Free finished transactions
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for( j <- 0 until NTILES ) {
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val finish = io.tiles(j).xact_finish
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free_arr.write(finish.bits.globalTransactionID, finish.valid)
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finish.ready := Bool(true)
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}
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// Forward memory responses from mem to tile
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val xrep_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
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val xrep_cnt_next = xrep_cnt + UFix(1)
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when (io.mem.resp_val) { xrep_cnt := xrep_cnt_next }
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val idx = io.mem.resp_tag
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val readys = Bits(width = NTILES)
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for( j <- 0 until NTILES ) {
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io.tiles(j).xact_rep.bits.ttype := getTransactionReplyType(ttype_arr.read(idx), sh_count_arr.read(idx))
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io.tiles(j).xact_rep.bits.tileTransactionID := tile_xact_id_arr.read(idx)
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io.tiles(j).xact_rep.bits.globalTransactionID := idx
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io.tiles(j).xact_rep_data.bits.data := io.mem.resp_data
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readys := Mux(xrep_cnt === UFix(0), io.tiles(j).xact_rep.ready && io.tiles(j).xact_rep_data.ready, io.tiles(j).xact_rep_data.ready)
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val this_rep_valid = UFix(j) === tile_id_arr.read(idx) && io.mem.resp_val
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io.tiles(j).xact_rep.valid := this_rep_valid && xrep_cnt === UFix(0)
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io.tiles(j).xact_rep_data.valid := this_rep_valid
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}
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// If there were a ready signal due to e.g. intervening network:
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//io.mem.resp_rdy := readys(tile_id_arr.read(idx)).xact_rep.ready
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// Pick a single request of these types to process
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//val xact_init_arb = (new Arbiter(NTILES)) { new TransactionInit() }
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//val probe_reply_arb = (new Arbiter(NTILES)) { new ProbeReply() }
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}
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}
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