riscv/rocket-chip
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tilelink2: do not depend on obsolete TL1 configuration

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This commit is contained in:
Wesley W. Terpstra
2016-11-17 14:07:53 -08:00
parent 8a0ecdaaad
commit dfc3a0dafb
6 changed files with 25 additions and 14 deletions
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9
src/main/scala/rocketchip/Configs.scala
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@ -41,8 +41,9 @@ class BasePlatformConfig extends Config(
case TLKey("MMIOtoEdge") =>
site(TLKey("L2toMMIO")).copy(dataBeats = edgeDataBeats)
case NExtTopInterrupts => 2
case SOCBusKey => SOCBusConfig(beatBytes = site(TLKey("L2toMMIO")).dataBitsPerBeat/8)
case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 4)
case SOCBusConfig => site(L1toL2Config)
case PeripheryBusConfig => TLBusConfig(beatBytes = 4)
case PeripheryBusArithmetic => true
// Note that PLIC asserts that this is > 0.
case AsyncDebugBus => false
case IncludeJtagDTM => false
@ -177,13 +178,13 @@ class WithJtagDTM extends Config (
class WithNoPeripheryArithAMO extends Config (
(pname, site, here) => pname match {
case PeripheryBusKey => PeripheryBusConfig(arithAMO = false, beatBytes = 4)
case PeripheryBusArithmetic => false
}
)
class With64BitPeriphery extends Config (
(pname, site, here) => pname match {
case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 8)
case PeripheryBusConfig => TLBusConfig(beatBytes = 8)
}
)