diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala
index 1111ab1d..737b5624 100644
--- a/src/main/scala/coreplex/BaseCoreplex.scala
+++ b/src/main/scala/coreplex/BaseCoreplex.scala
@@ -14,6 +14,11 @@ import uncore.converters._
 import rocket._
 import util._
 
+/** Widths of various points in the SoC */
+case class TLBusConfig(beatBytes: Int)
+case object CBusConfig extends Field[TLBusConfig]
+case object L1toL2Config extends Field[TLBusConfig]
+
 /** Number of memory channels */
 case object NMemoryChannels extends Field[Int]
 /** Number of banks per memory channel */
@@ -25,6 +30,8 @@ case object BootROMFile extends Field[String]
 
 trait HasCoreplexParameters {
   implicit val p: Parameters
+  lazy val cbusConfig = p(CBusConfig)
+  lazy val l1tol2Config = p(L1toL2Config)
   lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
   lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
   lazy val outerMemParams = p.alterPartial({ case TLId => "L2toMC" })
@@ -51,11 +58,11 @@ trait CoreplexNetwork extends HasCoreplexParameters {
   val module: CoreplexNetworkModule
 
   val l1tol2 = LazyModule(new TLXbar)
-  val l1tol2_beatBytes = p(TLKey("L2toMMIO")).dataBitsPerBeat/8
+  val l1tol2_beatBytes = l1tol2Config.beatBytes
   val l1tol2_lineBytes = p(CacheBlockBytes)
 
   val cbus = LazyModule(new TLXbar)
-  val cbus_beatBytes = p(XLen)/8
+  val cbus_beatBytes = cbusConfig.beatBytes
   val cbus_lineBytes = l1tol2_lineBytes
 
   val intBar = LazyModule(new IntXbar)
diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala
index 3a5a1d92..5237aa8e 100644
--- a/src/main/scala/coreplex/Configs.scala
+++ b/src/main/scala/coreplex/Configs.scala
@@ -92,6 +92,8 @@ class BaseCoreplexConfig extends Config (
       case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
       case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
                              log2Up(site(TLKey(site(TLId))).nClients)
+      case CBusConfig => TLBusConfig(beatBytes = site(XLen)/8)
+      case L1toL2Config => TLBusConfig(beatBytes = site(XLen)/8) // increase for more PCIe bandwidth
       case TLKey("L1toL2") => {
         val useMEI = site(NTiles) <= 1
         TileLinkParameters(
diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala
index 4dd230b4..453238a5 100644
--- a/src/main/scala/rocketchip/BaseTop.scala
+++ b/src/main/scala/rocketchip/BaseTop.scala
@@ -49,8 +49,8 @@ trait TopNetwork extends HasPeripheryParameters {
   val intBus = LazyModule(new IntXbar)
 
   peripheryBus.node :=
-    TLWidthWidget(p(SOCBusKey).beatBytes)(
-    TLAtomicAutomata(arithmetic = p(PeripheryBusKey).arithAMO)(
+    TLWidthWidget(socBusConfig.beatBytes)(
+    TLAtomicAutomata(arithmetic = peripheryBusArithmetic)(
     socBus.node))
 
   var coreplexMem = Seq[TLOutwardNode]()
diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala
index 847cfb6b..0db7091c 100644
--- a/src/main/scala/rocketchip/Configs.scala
+++ b/src/main/scala/rocketchip/Configs.scala
@@ -41,8 +41,9 @@ class BasePlatformConfig extends Config(
         case TLKey("MMIOtoEdge") =>
           site(TLKey("L2toMMIO")).copy(dataBeats = edgeDataBeats)
         case NExtTopInterrupts => 2
-        case SOCBusKey => SOCBusConfig(beatBytes = site(TLKey("L2toMMIO")).dataBitsPerBeat/8)
-        case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 4)
+        case SOCBusConfig => site(L1toL2Config)
+        case PeripheryBusConfig => TLBusConfig(beatBytes = 4)
+        case PeripheryBusArithmetic => true
         // Note that PLIC asserts that this is > 0.
         case AsyncDebugBus => false
         case IncludeJtagDTM => false
@@ -177,13 +178,13 @@ class WithJtagDTM extends Config (
 
 class WithNoPeripheryArithAMO extends Config (
   (pname, site, here) => pname match {
-    case PeripheryBusKey => PeripheryBusConfig(arithAMO = false, beatBytes = 4)
+    case PeripheryBusArithmetic => false
   }
 )
 
 class With64BitPeriphery extends Config (
   (pname, site, here) => pname match {
-    case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 8)
+    case PeripheryBusConfig => TLBusConfig(beatBytes = 8)
   }
 )
 
diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index 1a2dd8a6..8c5b7fa2 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -46,11 +46,10 @@ case object NExtTopInterrupts extends Field[Int]
 /** Source of RTC. First bundle is TopIO.extra, Second bundle is periphery.io.extra  **/
 case object RTCPeriod extends Field[Int]
 /* Specifies the periphery bus configuration */
-case class PeripheryBusConfig(arithAMO: Boolean, beatBytes: Int = 4)
-case object PeripheryBusKey extends Field[PeripheryBusConfig]
+case object PeripheryBusConfig extends Field[TLBusConfig]
+case object PeripheryBusArithmetic extends Field[Boolean]
 /* Specifies the SOC-bus configuration */
-case class SOCBusConfig(beatBytes: Int = 4)
-case object SOCBusKey extends Field[SOCBusConfig]
+case object SOCBusConfig extends Field[TLBusConfig]
 
 /* Specifies the data and id width at the chip boundary */
 case object EdgeDataBits extends Field[Int]
@@ -88,9 +87,10 @@ trait HasPeripheryParameters {
   lazy val nMemTLChannels  = if (tMemChannels == BusType.TL)  nMemChannels else 0
   lazy val edgeSlaveParams = p.alterPartial({ case TLId => "EdgetoSlave" })
   lazy val edgeMemParams = p.alterPartial({ case TLId => "MCtoEdge" })
-  lazy val peripheryBusConfig = p(PeripheryBusKey)
-  lazy val socBusConfig = p(SOCBusKey)
+  lazy val peripheryBusConfig = p(PeripheryBusConfig)
+  lazy val socBusConfig = p(SOCBusConfig)
   lazy val cacheBlockBytes = p(CacheBlockBytes)
+  lazy val peripheryBusArithmetic = p(PeripheryBusArithmetic)
 }
 
 /////
diff --git a/src/main/scala/uncore/tilelink2/Xbar.scala b/src/main/scala/uncore/tilelink2/Xbar.scala
index 6e2b64a0..5c32ca94 100644
--- a/src/main/scala/uncore/tilelink2/Xbar.scala
+++ b/src/main/scala/uncore/tilelink2/Xbar.scala
@@ -55,6 +55,7 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst) extends Lazy
         minLatency = seq.map(_.minLatency).min,
         endSinkId = outputIdRanges.map(_.end).max,
         managers = ManagerUnification(seq.flatMap { port =>
+          // println(s"${port.managers.map(_.name)} ${port.beatBytes} vs ${seq(0).managers.map(_.name)} ${seq(0).beatBytes}")
           require (port.beatBytes == seq(0).beatBytes)
           val fifoIdMapper = fifoIdFactory()
           port.managers map { manager => manager.copy(