riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2: do not depend on obsolete TL1 configuration

Browse Source
This commit is contained in:
Wesley W. Terpstra
2016-11-17 14:07:53 -08:00
parent 8a0ecdaaad
commit dfc3a0dafb
6 changed files with 25 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/rocketchip/BaseTop.scala
View File

@ -49,8 +49,8 @@ trait TopNetwork extends HasPeripheryParameters {
val intBus = LazyModule(new IntXbar)
peripheryBus.node :=
TLWidthWidget(p(SOCBusKey).beatBytes)(
TLAtomicAutomata(arithmetic = p(PeripheryBusKey).arithAMO)(
TLWidthWidget(socBusConfig.beatBytes)(
TLAtomicAutomata(arithmetic = peripheryBusArithmetic)(
socBus.node))
var coreplexMem = Seq[TLOutwardNode]()

9
src/main/scala/rocketchip/Configs.scala
View File

@ -41,8 +41,9 @@ class BasePlatformConfig extends Config(
case TLKey("MMIOtoEdge") =>
site(TLKey("L2toMMIO")).copy(dataBeats = edgeDataBeats)
case NExtTopInterrupts => 2
case SOCBusKey => SOCBusConfig(beatBytes = site(TLKey("L2toMMIO")).dataBitsPerBeat/8)
case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 4)
case SOCBusConfig => site(L1toL2Config)
case PeripheryBusConfig => TLBusConfig(beatBytes = 4)
case PeripheryBusArithmetic => true
// Note that PLIC asserts that this is > 0.
case AsyncDebugBus => false
case IncludeJtagDTM => false
@ -177,13 +178,13 @@ class WithJtagDTM extends Config (
class WithNoPeripheryArithAMO extends Config (
(pname, site, here) => pname match {
case PeripheryBusKey => PeripheryBusConfig(arithAMO = false, beatBytes = 4)
case PeripheryBusArithmetic => false
}
)
class With64BitPeriphery extends Config (
(pname, site, here) => pname match {
case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 8)
case PeripheryBusConfig => TLBusConfig(beatBytes = 8)
}
)

12
src/main/scala/rocketchip/Periphery.scala
View File

@ -46,11 +46,10 @@ case object NExtTopInterrupts extends Field[Int]
/** Source of RTC. First bundle is TopIO.extra, Second bundle is periphery.io.extra **/
case object RTCPeriod extends Field[Int]
/* Specifies the periphery bus configuration */
case class PeripheryBusConfig(arithAMO: Boolean, beatBytes: Int = 4)
case object PeripheryBusKey extends Field[PeripheryBusConfig]
case object PeripheryBusConfig extends Field[TLBusConfig]
case object PeripheryBusArithmetic extends Field[Boolean]
/* Specifies the SOC-bus configuration */
case class SOCBusConfig(beatBytes: Int = 4)
case object SOCBusKey extends Field[SOCBusConfig]
case object SOCBusConfig extends Field[TLBusConfig]
/* Specifies the data and id width at the chip boundary */
case object EdgeDataBits extends Field[Int]
@ -88,9 +87,10 @@ trait HasPeripheryParameters {
lazy val nMemTLChannels = if (tMemChannels == BusType.TL) nMemChannels else 0
lazy val edgeSlaveParams = p.alterPartial({ case TLId => "EdgetoSlave" })
lazy val edgeMemParams = p.alterPartial({ case TLId => "MCtoEdge" })
lazy val peripheryBusConfig = p(PeripheryBusKey)
lazy val socBusConfig = p(SOCBusKey)
lazy val peripheryBusConfig = p(PeripheryBusConfig)
lazy val socBusConfig = p(SOCBusConfig)
lazy val cacheBlockBytes = p(CacheBlockBytes)
lazy val peripheryBusArithmetic = p(PeripheryBusArithmetic)
}
/////