riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2: do not depend on obsolete TL1 configuration

Browse Source
This commit is contained in:
Wesley W. Terpstra
2016-11-17 14:07:53 -08:00
parent 8a0ecdaaad
commit dfc3a0dafb
6 changed files with 25 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/coreplex/Configs.scala
View File

@ -92,6 +92,8 @@ class BaseCoreplexConfig extends Config (
case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
log2Up(site(TLKey(site(TLId))).nClients)
case CBusConfig => TLBusConfig(beatBytes = site(XLen)/8)
case L1toL2Config => TLBusConfig(beatBytes = site(XLen)/8) // increase for more PCIe bandwidth
case TLKey("L1toL2") => {
val useMEI = site(NTiles) <= 1
TileLinkParameters(