riscv/rocket-chip
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This commit is contained in:
Andrew Waterman
2014-01-16 12:44:29 -08:00
parent d99ee1f9c2
commit dfc13236d1
6 changed files with 8 additions and 8 deletions
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2
chisel

Submodule chisel updated: 22ab4efe58...ae1d1de821

6
csrc/emulator.cc
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@ -94,7 +94,7 @@ int main(int argc, char** argv)
tile.Top__io_mem_req_data_ready = LIT<1>(mm->req_data_ready()); tile.Top__io_mem_req_data_ready = LIT<1>(mm->req_data_ready());
tile.Top__io_mem_resp_valid = LIT<1>(mm->resp_valid()); tile.Top__io_mem_resp_valid = LIT<1>(mm->resp_valid());
tile.Top__io_mem_resp_bits_tag = LIT<64>(mm->resp_tag()); tile.Top__io_mem_resp_bits_tag = LIT<64>(mm->resp_tag());
memcpy(&tile.Top__io_mem_resp_bits_data, mm->resp_data(), tile.Top__io_mem_resp_bits_data.width()/8); memcpy(tile.Top__io_mem_resp_bits_data.values, mm->resp_data(), tile.Top__io_mem_resp_bits_data.width()/8);
tile.clock_lo(LIT<1>(0)); tile.clock_lo(LIT<1>(0));
@ -105,7 +105,7 @@ int main(int argc, char** argv)
tile.Top__io_mem_req_cmd_bits_tag.lo_word(), tile.Top__io_mem_req_cmd_bits_tag.lo_word(),
tile.Top__io_mem_req_data_valid.lo_word(), tile.Top__io_mem_req_data_valid.lo_word(),
&tile.Top__io_mem_req_data_bits_data.values[0], tile.Top__io_mem_req_data_bits_data.values,
tile.Top__io_mem_resp_ready.to_bool() tile.Top__io_mem_resp_ready.to_bool()
); );
@ -120,7 +120,7 @@ int main(int argc, char** argv)
tile.Top__io_host_in_bits = LIT<64>(htif_in_bits); tile.Top__io_host_in_bits = LIT<64>(htif_in_bits);
if (tile.Top__io_host_out_valid.to_bool()) if (tile.Top__io_host_out_valid.to_bool())
htif->send(&tile.Top__io_host_out_bits.values[0], htif_bits/8); htif->send(tile.Top__io_host_out_bits.values, htif_bits/8);
tile.Top__io_host_out_ready = LIT<1>(1); tile.Top__io_host_out_ready = LIT<1>(1);
} }

2
riscv-tests

Submodule riscv-tests updated: b374fd10b2...d710b4ba5d

2
riscv-tools

Submodule riscv-tools updated: 20ff67d56c...fb38473be6

2
rocket

Submodule rocket updated: 6554ed321c...2249bbfbde

2
uncore

Submodule uncore updated: 2a21e8435a...a58265755f