riscv/rocket-chip
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Better abstraction of data bundles

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This commit is contained in:
Henry Cook 2012-02-25 12:56:09 -08:00
parent 4fa31b300b
commit df97de0fd3
1 changed files with 18 additions and 7 deletions
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25
rocket/src/main/scala/coherence.scala
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@ -4,13 +4,27 @@ import Chisel._
import Constants._ import Constants._
import hwacha.GenArray import hwacha.GenArray
class HubMemReq extends Bundle {
val rw = Bool()
val addr = UFix(width = PADDR_BITS-OFFSET_BITS)
val tag = Bits(width = GLOBAL_XACT_ID_BITS)
// Figure out which data-in port to pull from
val data_idx = Bits(width = TILE_ID_BITS)
val is_probe_rep = Bool()
}
class MemData extends Bundle {
val data = Bits(width = MEM_DATA_BITS)
}
class TransactionInit extends Bundle { class TransactionInit extends Bundle {
val ttype = Bits(width = TTYPE_BITS) val ttype = Bits(width = TTYPE_BITS)
val tileTransactionID = Bits(width = TILE_XACT_ID_BITS) val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
val address = Bits(width = PADDR_BITS) val address = Bits(width = PADDR_BITS)
val data = Bits(width = MEM_DATA_BITS)
} }
class TransactionInitData extends MemData
class TransactionAbort extends Bundle { class TransactionAbort extends Bundle {
val tileTransactionID = Bits(width = TILE_XACT_ID_BITS) val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
} }
@ -27,9 +41,7 @@ class ProbeReply extends Bundle {
val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS) val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
} }
class ProbeReplyData extends Bundle { class ProbeReplyData extends MemData
val data = Bits(width = MEM_DATA_BITS)
}
class TransactionReply extends Bundle { class TransactionReply extends Bundle {
val ttype = Bits(width = TTYPE_BITS) val ttype = Bits(width = TTYPE_BITS)
@ -37,9 +49,7 @@ class TransactionReply extends Bundle {
val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS) val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
} }
class TransactionReplyData extends Bundle { class TransactionReplyData extends MemData
val data = Bits(width = MEM_DATA_BITS)
}
class TransactionFinish extends Bundle { class TransactionFinish extends Bundle {
val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS) val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
@ -47,6 +57,7 @@ class TransactionFinish extends Bundle {
class ioTileLink extends Bundle { class ioTileLink extends Bundle {
val xact_init = (new ioDecoupled) { new TransactionInit() }.flip val xact_init = (new ioDecoupled) { new TransactionInit() }.flip
val xact_init_data = (new ioDecoupled) { new TransactionInitData() }.flip
val xact_abort = (new ioDecoupled) { new TransactionAbort() } val xact_abort = (new ioDecoupled) { new TransactionAbort() }
val probe_req = (new ioDecoupled) { new ProbeRequest() } val probe_req = (new ioDecoupled) { new ProbeRequest() }
val probe_rep = (new ioDecoupled) { new ProbeReply() }.flip val probe_rep = (new ioDecoupled) { new ProbeReply() }.flip