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debug: Make it easier to override parts of the Default Debug Config (#655)

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* Handle single-step with a pipeline stall, not a flush

The pipeline flush approach broke when I changed the pipeline stage
the flush happens from

* debug: Make it easier to override parts of the Default Debug Config

* Fix typo in Debug code generation

abstractGeneratedI should be abstractGeneratedS when pulling out the opcode.
This doesn't actually break anything, but fix it for clarity.
This commit is contained in:
Megan Wachs 2017-04-06 10:33:17 -07:00 committed by GitHub
parent 5c458322b5
commit df5caba7bf
2 changed files with 26 additions and 37 deletions
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2
src/main/scala/coreplex/Configs.scala
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@ -22,7 +22,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
case BuildCore => (p: Parameters) => new Rocket()(p) case BuildCore => (p: Parameters) => new Rocket()(p)
case RocketCrossing => Synchronous case RocketCrossing => Synchronous
case RocketTilesKey => Nil case RocketTilesKey => Nil
case DMKey => new DefaultDebugModuleConfig(site(XLen)) case DMKey => DefaultDebugModuleConfig(site(XLen))
case NTiles => site(RocketTilesKey).size case NTiles => site(RocketTilesKey).size
case CBusConfig => TLBusConfig(beatBytes = site(XLen)/8) case CBusConfig => TLBusConfig(beatBytes = site(XLen)/8)
case L1toL2Config => TLBusConfig(beatBytes = site(XLen)/8) // increase for more PCIe bandwidth case L1toL2Config => TLBusConfig(beatBytes = site(XLen)/8) // increase for more PCIe bandwidth

61
src/main/scala/uncore/devices/debug/Debug.scala
View File

@ -109,22 +109,22 @@ import DebugAbstractCommandType._
**/ **/
case class DebugModuleConfig ( case class DebugModuleConfig (
nDMIAddrSize : Int, nDMIAddrSize : Int = 7,
nProgramBufferWords: Int, nProgramBufferWords: Int = 16,
nAbstractDataWords : Int, nAbstractDataWords : Int = 4,
nScratch : Int, nScratch : Int = 1,
//TODO: Use diplomacy to decide if you want this. //TODO: Use diplomacy to decide if you want this.
hasBusMaster : Boolean, hasBusMaster : Boolean = false,
hasAccess128 : Boolean, hasAccess128 : Boolean = false,
hasAccess64 : Boolean, hasAccess64 : Boolean = false,
hasAccess32 : Boolean, hasAccess32 : Boolean = false,
hasAccess16 : Boolean, hasAccess16 : Boolean = false,
hasAccess8 : Boolean, hasAccess8 : Boolean = false,
nSerialPorts : Int, nSerialPorts : Int = 0,
supportQuickAccess : Boolean, supportQuickAccess : Boolean = false,
supportHartArray : Boolean, supportHartArray : Boolean = false,
hartIdToHartSel : (UInt) => UInt, hartIdToHartSel : (UInt) => UInt = (x:UInt) => x,
hartSelToHartId : (UInt) => UInt hartSelToHartId : (UInt) => UInt = (x:UInt) => x
) { ) {
if (hasBusMaster == false){ if (hasBusMaster == false){
@ -148,26 +148,15 @@ case class DebugModuleConfig (
} }
class DefaultDebugModuleConfig (val xlen:Int /*TODO , val configStringAddr: Int*/) object DefaultDebugModuleConfig {
extends DebugModuleConfig(
nDMIAddrSize = 7, def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleConfig = {
nProgramBufferWords = 16, new DebugModuleConfig().copy(
// TODO use less for small XLEN? nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4)
nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4), )
nScratch = 1, }
hasBusMaster = false, }
hasAccess128 = false,
hasAccess64 = false,
hasAccess32 = false,
hasAccess16 = false,
hasAccess8 = false,
nSerialPorts = 0,
supportQuickAccess = false,
supportHartArray = false,
// TODO configStringAddr = configStringAddr
hartIdToHartSel = (x: UInt) => x,
hartSelToHartId = (x: UInt) => x
)
case object DMKey extends Field[DebugModuleConfig] case object DMKey extends Field[DebugModuleConfig]
@ -840,7 +829,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
abstractGeneratedI.rs1 := 0.U abstractGeneratedI.rs1 := 0.U
abstractGeneratedI.imm := DATA.U abstractGeneratedI.imm := DATA.U
abstractGeneratedS.opcode := ((new GeneratedI()).fromBits(rocket.Instructions.SW.value.U)).opcode abstractGeneratedS.opcode := ((new GeneratedS()).fromBits(rocket.Instructions.SW.value.U)).opcode
abstractGeneratedS.immlo := (DATA & 0x1F).U abstractGeneratedS.immlo := (DATA & 0x1F).U
abstractGeneratedS.funct3 := accessRegisterCommandReg.size abstractGeneratedS.funct3 := accessRegisterCommandReg.size
abstractGeneratedS.rs1 := 0.U abstractGeneratedS.rs1 := 0.U