riscv/rocket-chip
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don't make MIFTagBits a computed parameter

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This commit is contained in:
Howard Mao 2016-05-07 21:26:03 -07:00
parent 3b0e9167fa
commit df479d7935
3 changed files with 26 additions and 15 deletions
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27
csrc/vcs_main.rocketTestHarness.cc
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@ -101,17 +101,27 @@ void memory_tick(
for (size_t i = 0; i < mmc->get_word_size()/sizeof(uint32_t); i++) for (size_t i = 0; i < mmc->get_word_size()/sizeof(uint32_t); i++)
write_data[i] = vc_4stVectorRef(w_data)[i].d; write_data[i] = vc_4stVectorRef(w_data)[i].d;
uint32_t aw_id_val, ar_id_val;
if (MEM_ID_BITS == 1) {
aw_id_val = vc_getScalar(aw_id);
ar_id_val = vc_getScalar(ar_id);
} else {
aw_id_val = vc_4stVectorRef(aw_id)->d;
ar_id_val = vc_4stVectorRef(ar_id)->d;
}
mmc->tick mmc->tick
( (
vc_getScalar(ar_valid), vc_getScalar(ar_valid),
vc_4stVectorRef(ar_addr)->d - MEM_BASE, vc_4stVectorRef(ar_addr)->d - MEM_BASE,
vc_4stVectorRef(ar_id)->d, ar_id_val,
vc_4stVectorRef(ar_size)->d, vc_4stVectorRef(ar_size)->d,
vc_4stVectorRef(ar_len)->d, vc_4stVectorRef(ar_len)->d,
vc_getScalar(aw_valid), vc_getScalar(aw_valid),
vc_4stVectorRef(aw_addr)->d - MEM_BASE, vc_4stVectorRef(aw_addr)->d - MEM_BASE,
vc_4stVectorRef(aw_id)->d, aw_id_val,
vc_4stVectorRef(aw_size)->d, vc_4stVectorRef(aw_size)->d,
vc_4stVectorRef(aw_len)->d, vc_4stVectorRef(aw_len)->d,
@ -137,17 +147,22 @@ void memory_tick(
d[0].d = mmc->b_resp(); d[0].d = mmc->b_resp();
vc_put4stVector(b_resp, d); vc_put4stVector(b_resp, d);
d[0].c = 0;
d[0].d = mmc->r_resp();
vc_put4stVector(r_resp, d);
if (MEM_ID_BITS > 1) {
d[0].c = 0; d[0].c = 0;
d[0].d = mmc->b_id(); d[0].d = mmc->b_id();
vc_put4stVector(b_id, d); vc_put4stVector(b_id, d);
d[0].c = 0;
d[0].d = mmc->r_resp();
vc_put4stVector(r_resp, d);
d[0].c = 0; d[0].c = 0;
d[0].d = mmc->r_id(); d[0].d = mmc->r_id();
vc_put4stVector(r_id, d); vc_put4stVector(r_id, d);
} else {
vc_putScalar(b_id, mmc->b_id());
vc_putScalar(r_id, mmc->r_id());
}
for (size_t i = 0; i < mmc->get_word_size()/sizeof(uint32_t); i++) for (size_t i = 0; i < mmc->get_word_size()/sizeof(uint32_t); i++)
{ {

6
src/main/scala/Configs.scala
View File

@ -102,11 +102,7 @@ class DefaultConfig extends Config (
case PPNBits => site(PAddrBits) - site(PgIdxBits) case PPNBits => site(PAddrBits) - site(PgIdxBits)
case VAddrBits => site(VPNBits) + site(PgIdxBits) case VAddrBits => site(VPNBits) + site(PgIdxBits)
case ASIdBits => 7 case ASIdBits => 7
case MIFTagBits => Dump("MIF_TAG_BITS", case MIFTagBits => Dump("MIF_TAG_BITS", 5)
// Bits needed at the L2 agent
log2Up(site(NAcquireTransactors)+2) +
// Bits added by NASTI interconnect
log2Up(site(NBanksPerMemoryChannel)))
case MIFDataBits => Dump("MIF_DATA_BITS", 64) case MIFDataBits => Dump("MIF_DATA_BITS", 64)
case MIFAddrBits => Dump("MIF_ADDR_BITS", case MIFAddrBits => Dump("MIF_ADDR_BITS",
site(PAddrBits) - site(CacheBlockOffsetBits)) site(PAddrBits) - site(CacheBlockOffsetBits))

2
uncore

@ -1 +1 @@
Subproject commit f236b5fa0dbc3ab488b5ac021862808f11361524 Subproject commit 143ce453a489ffae7dc3f65db2d50a7dc5d18b7f