riscv/rocket-chip
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don't make MIFTagBits a computed parameter

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Howard Mao committed 2016-05-08 11:04:58 -07:00
1 parent 3b0e9167fa
commit df479d7935
3 files changed
+26 -15
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src/main/scala/Configs.scala
+1 -5
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@@ -102,11 +102,7 @@ class DefaultConfig extends Config (
case PPNBits => site(PAddrBits) - site(PgIdxBits)
case VAddrBits => site(VPNBits) + site(PgIdxBits)
case ASIdBits => 7
case MIFTagBits => Dump("MIF_TAG_BITS",
// Bits needed at the L2 agent
log2Up(site(NAcquireTransactors)+2) +
// Bits added by NASTI interconnect
log2Up(site(NBanksPerMemoryChannel)))
case MIFTagBits => Dump("MIF_TAG_BITS", 5)
case MIFDataBits => Dump("MIF_DATA_BITS", 64)
case MIFAddrBits => Dump("MIF_ADDR_BITS",
site(PAddrBits) - site(CacheBlockOffsetBits))