riscv/rocket-chip
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axi4: SRAM can emulate incompletely populated memory

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This commit is contained in:
Wesley W. Terpstra
2017-07-07 21:07:08 -07:00
parent b2cc4b99ed
commit df44b23956
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/amba/axi4/SRAM.scala
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@@ -7,11 +7,11 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, errors: Seq[AddressSet] = Nil)(implicit p: Parameters) extends LazyModule
{ {
val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters( val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
Seq(AXI4SlaveParameters( Seq(AXI4SlaveParameters(
address = List(address), address = List(address) ++ errors,
regionType = RegionType.UNCACHED, regionType = RegionType.UNCACHED,
executable = executable, executable = executable,
supportsRead = TransferSizes(1, beatBytes), supportsRead = TransferSizes(1, beatBytes),