From df44b23956007162db32719446c3ca1f598354cb Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 7 Jul 2017 21:07:08 -0700 Subject: [PATCH] axi4: SRAM can emulate incompletely populated memory --- src/main/scala/amba/axi4/SRAM.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/amba/axi4/SRAM.scala b/src/main/scala/amba/axi4/SRAM.scala index 72e580c1..680c0098 100644 --- a/src/main/scala/amba/axi4/SRAM.scala +++ b/src/main/scala/amba/axi4/SRAM.scala @@ -7,11 +7,11 @@ import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ -class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule +class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, errors: Seq[AddressSet] = Nil)(implicit p: Parameters) extends LazyModule { val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters( Seq(AXI4SlaveParameters( - address = List(address), + address = List(address) ++ errors, regionType = RegionType.UNCACHED, executable = executable, supportsRead = TransferSizes(1, beatBytes),