riscv/rocket-chip
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[rocketchip] avoid pending merge conflict]

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This commit is contained in:
Henry Cook
2016-09-19 13:24:01 -07:00
parent ddcf1b4099
commit df442ed82c
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/rocketchip/BaseTop.scala
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@@ -61,8 +61,6 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
val coreplex = p(BuildCoreplex)(p, outer.c)
val io: B = b(coreplex)
io.success := coreplex.io.success
val mmioNetwork =
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:ext"))(
p.alterPartial({ case TLId => "L2toMMIO" })))
@@ -80,4 +78,6 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
println("Generated Configuration String")
println(p(ConfigString))
ConfigStringOutput.contents = Some(p(ConfigString))
io.success := coreplex.io.success
}