riscv/rocket-chip
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Quick change to work with new Width class.

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This commit is contained in:
Jim Lawson 2014-06-13 12:00:50 -07:00
parent dab675b231
commit de32595fba
2 changed files with 3 additions and 3 deletions
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2
rocket/src/main/scala/decode.scala
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@ -9,7 +9,7 @@ object DecodeLogic
val lit = b.litOf val lit = b.litOf
if (lit.isZ) { if (lit.isZ) {
var (bits, mask, swidth) = Literal.parseLit(lit.toString) var (bits, mask, swidth) = Literal.parseLit(lit.toString)
new Term(BigInt(bits, 2), BigInt(2).pow(lit.width)-(BigInt(mask, 2)+1)) new Term(BigInt(bits, 2), BigInt(2).pow(lit.needWidth())-(BigInt(mask, 2)+1))
} else { } else {
new Term(lit.value) new Term(lit.value)
} }

4
rocket/src/main/scala/util.scala
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@ -163,8 +163,8 @@ class FlowThroughSerializer[T <: HasTileLinkData](gen: LogicalNetworkIO[T], n: I
val cnt = UInt(OUTPUT, log2Up(n)) val cnt = UInt(OUTPUT, log2Up(n))
val done = Bool(OUTPUT) val done = Bool(OUTPUT)
} }
require(io.in.bits.payload.data.width % n == 0) require(io.in.bits.payload.data.needWidth() % n == 0)
val narrowWidth = io.in.bits.payload.data.width / n val narrowWidth = io.in.bits.payload.data.needWidth() / n
val cnt = Reg(init=UInt(0, width = log2Up(n))) val cnt = Reg(init=UInt(0, width = log2Up(n)))
val wrap = cnt === UInt(n-1) val wrap = cnt === UInt(n-1)
val rbits = Reg(init=io.in.bits) val rbits = Reg(init=io.in.bits)