riscv/rocket-chip
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get rid of more global constants

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This commit is contained in:
Andrew Waterman 2012-11-25 04:24:25 -08:00
parent c036cdc1ea
commit de2f28193a
6 changed files with 7 additions and 13 deletions
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8
rocket/src/main/scala/consts.scala
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@ -5,6 +5,7 @@ import Chisel._
import scala.math._ import scala.math._
trait ScalarOpConstants { trait ScalarOpConstants {
val SZ_BR = 3
val BR_X = Bits("b???", 3) val BR_X = Bits("b???", 3)
val BR_EQ = Bits(0, 3) val BR_EQ = Bits(0, 3)
val BR_NE = Bits(1, 3) val BR_NE = Bits(1, 3)
@ -105,13 +106,6 @@ abstract trait RocketDcacheConstants extends uncore.constants.CacheConstants wit
require(log2Up(OFFSET_BITS) <= uncore.Constants.X_INIT_SUBWORD_ADDR_BITS) require(log2Up(OFFSET_BITS) <= uncore.Constants.X_INIT_SUBWORD_ADDR_BITS)
} }
trait TLBConstants {
val BTB_ENTRIES = 8
val ITLB_ENTRIES = 8
val DTLB_ENTRIES = 16
val VITLB_ENTRIES = 4
}
trait VectorOpConstants { trait VectorOpConstants {
val VEC_X = Bits("b??", 2).toUFix val VEC_X = Bits("b??", 2).toUFix
val VEC_FN_N = UFix(0, 2) val VEC_FN_N = UFix(0, 2)

2
rocket/src/main/scala/ctrl.scala
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@ -43,7 +43,7 @@ class ioCtrlDpath extends Bundle()
// inputs from datapath // inputs from datapath
val inst = Bits(INPUT, 32); val inst = Bits(INPUT, 32);
val jalr_eq = Bool(INPUT) val jalr_eq = Bool(INPUT)
val ex_br_type = Bits(OUTPUT, 3) val ex_br_type = Bits(OUTPUT, SZ_BR)
val ex_br_taken = Bool(INPUT) val ex_br_taken = Bool(INPUT)
val div_rdy = Bool(INPUT); val div_rdy = Bool(INPUT);
val div_result_val = Bool(INPUT); val div_result_val = Bool(INPUT);

2
rocket/src/main/scala/dpath.scala
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@ -216,7 +216,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
io.ptw.status := pcr.io.status io.ptw.status := pcr.io.status
// branch resolution logic // branch resolution logic
io.ctrl.jalr_eq := ex_rs1 === id_pc.toFix && ex_reg_inst(11,0) === UFix(0) io.ctrl.jalr_eq := ex_rs1 === id_pc.toFix && ex_reg_inst(21,10) === UFix(0)
io.ctrl.ex_br_taken := io.ctrl.ex_br_taken :=
Mux(io.ctrl.ex_br_type === BR_EQ, ex_rs1 === ex_rs2, Mux(io.ctrl.ex_br_type === BR_EQ, ex_rs1 === ex_rs2,
Mux(io.ctrl.ex_br_type === BR_NE, ex_rs1 != ex_rs2, Mux(io.ctrl.ex_br_type === BR_NE, ex_rs1 != ex_rs2,

5
rocket/src/main/scala/icache.scala
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@ -7,6 +7,7 @@ import uncore._
import Util._ import Util._
case class ICacheConfig(sets: Int, assoc: Int, co: CoherencePolicyWithUncached, case class ICacheConfig(sets: Int, assoc: Int, co: CoherencePolicyWithUncached,
ntlb: Int = 8, nbtb: Int = 8,
code: Code = new IdentityCode) code: Code = new IdentityCode)
{ {
val w = 1 val w = 1
@ -56,9 +57,9 @@ class Frontend(implicit c: ICacheConfig) extends Component
val mem = new ioUncachedRequestor val mem = new ioUncachedRequestor
} }
val btb = new rocketDpathBTB(BTB_ENTRIES) val btb = new rocketDpathBTB(c.nbtb)
val icache = new ICache val icache = new ICache
val tlb = new TLB(ITLB_ENTRIES) val tlb = new TLB(c.ntlb)
val s1_pc = Reg() { UFix() } val s1_pc = Reg() { UFix() }
val s1_same_block = Reg() { Bool() } val s1_same_block = Reg() { Bool() }

2
rocket/src/main/scala/nbdcache.scala
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@ -7,7 +7,7 @@ import uncore._
import Util._ import Util._
case class DCacheConfig(sets: Int, ways: Int, co: CoherencePolicy, case class DCacheConfig(sets: Int, ways: Int, co: CoherencePolicy,
nmshr: Int, nrpq: Int, nsdq: Int, nmshr: Int, nrpq: Int, nsdq: Int, ntlb: Int,
reqtagbits: Int = -1, databits: Int = -1) reqtagbits: Int = -1, databits: Int = -1)
{ {
require(isPow2(sets)) require(isPow2(sets))

1
rocket/src/main/scala/package.scala
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@ -13,7 +13,6 @@ object Constants extends
InterruptConstants with InterruptConstants with
RocketDcacheConstants with RocketDcacheConstants with
VectorOpConstants with VectorOpConstants with
TLBConstants with
uncore.constants.MemoryInterfaceConstants uncore.constants.MemoryInterfaceConstants
{ {
val START_ADDR = 0x2000 val START_ADDR = 0x2000