riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

further generalize fpga/vlsi builds

Browse Source
This commit is contained in:
Yunsup Lee committed 2014-09-08 00:21:57 -07:00
1 parent 3175a40509
commit ddfd3ce968
8 files changed
+45 -48
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

vsrc/rocketTestHarness.v
+1 -1
View File
@@ -112,7 +112,7 @@ module rocketTestHarness;
wire #0.1 mem_bk_in_valid_delay = mem_bk_in_valid;
wire mem_bk_out_valid_delay; assign #0.1 mem_bk_out_valid = mem_bk_out_valid_delay;
`TOP dut
Top dut
(
.clk(clk),
.reset(reset),