further generalize fpga/vlsi builds

2014-09-08 00:21:57 -07:00
parent 3175a40509
commit ddfd3ce968
8 changed files with 45 additions and 48 deletions
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@ -43,7 +43,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet
 	-e vcs_main \
 	$(RISCV)/lib/libfesvr.so \
 	$(sim_dir)/libdramsim.a \
-	+define+TOP=$(MODEL) \
 	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
 	+define+PRINTF_COND=rocketTestHarness.verbose \
 	+libext+.v \