riscv/rocket-chip
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further generalize fpga/vlsi builds

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This commit is contained in:
Yunsup Lee
2014-09-08 00:21:57 -07:00
parent 3175a40509
commit ddfd3ce968
8 changed files with 45 additions and 48 deletions
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5
vsim/Makefile
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@ -11,10 +11,13 @@ default: all
base_dir = $(abspath ..)
generated_dir = $(abspath ./generated-src)
vlsi_mem_gen = $(base_dir)/vsim/vlsi_mem_gen
mem_gen = $(base_dir)/vsim/vlsi_mem_gen
sim_dir = .
output_dir = $(sim_dir)/output
BACKEND = rocketchip.RocketChipBackend
CONFIG = DefaultVLSIConfig
include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag
include $(base_dir)/vsim/Makefrag-sim