riscv/rocket-chip
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further generalize fpga/vlsi builds

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This commit is contained in:
Yunsup Lee
2014-09-08 00:21:57 -07:00
parent 3175a40509
commit ddfd3ce968
8 changed files with 45 additions and 48 deletions
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4
fsim/Makefrag
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@ -6,8 +6,7 @@
# Verilog sources
sim_vsrcs = \
$(generated_dir)/$(FPGAMODEL).v \
$(generated_dir)/$(FPGAMODEL)Mem.v \
$(generated_dir)/$(MODEL).v \
$(generated_dir)/memdessertMemDessert.v \
$(base_dir)/vsrc/const.vh \
$(base_dir)/vsrc/rocketTestHarness.v \
@ -45,7 +44,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet
$(RISCV)/lib/libfesvr.so \
$(sim_dir)/libdramsim.a \
+define+FPGA \
+define+TOP=$(FPGAMODEL) \
+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
+define+PRINTF_COND=rocketTestHarness.verbose \
+libext+.v \