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tilelink2: add an executable manager parameter

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This commit is contained in:
Wesley W. Terpstra 2016-09-14 18:08:49 -07:00
parent 9442958d67
commit ddd93871d8
2 changed files with 8 additions and 4 deletions
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5
src/main/scala/uncore/tilelink2/Parameters.scala
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@ -63,7 +63,7 @@ case class TransferSizes(min: Int, max: Int)
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) = def intersect(x: TransferSizes) =
if (x.max < min || min < x.max) TransferSizes.none if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
} }
@ -103,6 +103,8 @@ case class TLManagerParameters(
address: Seq[AddressSet], address: Seq[AddressSet],
sinkId: IdRange = IdRange(0, 1), sinkId: IdRange = IdRange(0, 1),
regionType: RegionType.T = RegionType.GET_EFFECTS, regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false, // processor can execute from this memory
nodePath: Seq[TLBaseNode] = Seq(),
// Supports both Acquire+Release+Finish of these sizes // Supports both Acquire+Release+Finish of these sizes
supportsAcquire: TransferSizes = TransferSizes.none, supportsAcquire: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none,
@ -208,6 +210,7 @@ case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes
case class TLClientParameters( case class TLClientParameters(
sourceId: IdRange = IdRange(0,1), sourceId: IdRange = IdRange(0,1),
nodePath: Seq[TLBaseNode] = Seq(),
// Supports both Probe+Grant of these sizes // Supports both Probe+Grant of these sizes
supportsProbe: TransferSizes = TransferSizes.none, supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none,

1
src/main/scala/uncore/tilelink2/SRAM.scala
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@ -9,6 +9,7 @@ class TLRAM(address: AddressSet, beatBytes: Int = 4) extends LazyModule
val node = TLManagerNode(beatBytes, TLManagerParameters( val node = TLManagerNode(beatBytes, TLManagerParameters(
address = List(address), address = List(address),
regionType = RegionType.UNCACHED, regionType = RegionType.UNCACHED,
executable = true,
supportsGet = TransferSizes(1, beatBytes), supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes),