riscv/rocket-chip
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fix up FPU connection

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This commit is contained in:
Howard Mao 2015-12-01 18:14:58 -08:00
parent 08f77ca90d
commit dcca0b1d86
1 changed files with 22 additions and 23 deletions
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23
rocket/src/main/scala/tile.scala
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@ -13,15 +13,15 @@ case object BuildRoCC extends Field[Seq[RoccParameters]]
case class RoccParameters( case class RoccParameters(
opcodes: OpcodeSet, opcodes: OpcodeSet,
generator: Parameters => RoCC, generator: Parameters => RoCC,
nMemChannels: Int = 1) nMemChannels: Int = 1,
useFPU: Boolean = false)
abstract class Tile(resetSignal: Bool = null) abstract class Tile(resetSignal: Bool = null)
(implicit p: Parameters) extends Module(_reset = resetSignal) { (implicit p: Parameters) extends Module(_reset = resetSignal) {
val buildRocc = p(BuildRoCC) val buildRocc = p(BuildRoCC)
val usingRocc = !buildRocc.isEmpty val usingRocc = !buildRocc.isEmpty
val nRocc = buildRocc.size val nRocc = buildRocc.size
val roccUseFPU = p(RoccUseFPU) val nFPUPorts = buildRocc.filter(_.useFPU).size
val nFPUPorts = roccUseFPU.filter(useFPU => useFPU).size
val nDCachePorts = 2 + nRocc val nDCachePorts = 2 + nRocc
val nPTWPorts = 2 + 3 * nRocc val nPTWPorts = 2 + 3 * nRocc
val nCachedTileLinkPorts = 1 val nCachedTileLinkPorts = 1
@ -73,10 +73,9 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
val cmdRouter = Module(new RoccCommandRouter(roccOpcodes)) val cmdRouter = Module(new RoccCommandRouter(roccOpcodes))
cmdRouter.io.in <> core.io.rocc.cmd cmdRouter.io.in <> core.io.rocc.cmd
val roccs = buildRocc.zipWithIndex.map { val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) =>
case (RoccParameters(_, generator, nchannels), i) => val rocc = accelParams.generator(
val accelParams = p.alterPartial({ case RoccNMemChannels => nchannels }) p.alterPartial({ case RoccNMemChannels => accelParams.nMemChannels }))
val rocc = generator(accelParams)
val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams)) val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
rocc.io.cmd <> cmdRouter.io.out(i) rocc.io.cmd <> cmdRouter.io.out(i)
rocc.io.s := core.io.rocc.s rocc.io.s := core.io.rocc.s
@ -93,12 +92,12 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
if (nFPUPorts > 0) { if (nFPUPorts > 0) {
fpuOpt.foreach { fpu => fpuOpt.foreach { fpu =>
val fpArb = Module(new InOrderArbiter(new FPInput, new FPResult, nFPUPorts)) val fpArb = Module(new InOrderArbiter(new FPInput, new FPResult, nFPUPorts))
val fp_roccs = roccs.zip(roccUseFPU) val fp_roccs = roccs.zip(buildRocc)
.filter { case (_, useFPU) => useFPU } .filter { case (_, params) => params.useFPU }
.map { case (rocc, _) => rocc } .map { case (rocc, _) => rocc.io }
fpArb.io.in_req <> fp_roccs.map(_.io.fpu_req) fpArb.io.in_req <> fp_roccs.map(_.fpu_req)
fp_roccs.zip(fpArb.io.in_resp).foreach { fp_roccs.zip(fpArb.io.in_resp).foreach {
case (rocc, fpu_resp) => rocc.io.fpu_resp <> fpu_resp case (rocc, fpu_resp) => rocc.fpu_resp <> fpu_resp
} }
fpu.io.cp_req <> fpArb.io.out_req fpu.io.cp_req <> fpArb.io.out_req
fpArb.io.out_resp <> fpu.io.cp_resp fpArb.io.out_resp <> fpu.io.cp_resp