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PositionalMultiQueue: work around vcs Lint report

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Lint-[PCTIO-L] Ports coerced to inout
rocket-chip/vsim/generated-src/unittest.UncoreUnitTestConfig.v, 127524
"io_deq_0_valid"
  Port "io_deq_0_valid" declared as output in module "PositionalMultiQueue_16"
  may need to be inout. Coercing to inout.
This commit is contained in:
Wesley W. Terpstra 2016-10-06 15:34:13 -07:00
parent 5d905a5310
commit dcb9383568
1 changed files with 13 additions and 10 deletions
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23
src/main/scala/util/PositionalMultiQueue.scala
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@ -47,6 +47,9 @@ class PositionalMultiQueue[T <: Data](params: PositionalMultiQueueParameters[T],
guard(io.enq.bits.pos) := Bool(true) guard(io.enq.bits.pos) := Bool(true)
} }
val deq = Wire(io.deq)
io.deq <> deq
val waySelect = UIntToOH(io.enq.bits.way, params.ways) val waySelect = UIntToOH(io.enq.bits.way, params.ways)
for (i <- 0 until params.ways) { for (i <- 0 until params.ways) {
val enq = io.enq.fire() && waySelect(i) val enq = io.enq.fire() && waySelect(i)
@ -62,22 +65,22 @@ class PositionalMultiQueue[T <: Data](params: PositionalMultiQueueParameters[T],
} }
if (combinational) { if (combinational) {
io.deq(i).valid := !empty(i) || enq deq(i).valid := !empty(i) || enq
io.deq(i).bits.pos := Mux(empty(i), io.enq.bits.pos, head(i)) deq(i).bits.pos := Mux(empty(i), io.enq.bits.pos, head(i))
io.deq(i).bits.data := Mux(empty(i), io.enq.bits.data, data(head(i))) deq(i).bits.data := Mux(empty(i), io.enq.bits.data, data(head(i)))
} else { } else {
io.deq(i).valid := !empty(i) deq(i).valid := !empty(i)
io.deq(i).bits.pos := head(i) deq(i).bits.pos := head(i)
io.deq(i).bits.data := data(head(i)) deq(i).bits.data := data(head(i))
} }
when (io.deq(i).fire()) { when (deq(i).fire()) {
head(i) := Mux(last, io.enq.bits.pos, next(head(i))) head(i) := Mux(last, io.enq.bits.pos, next(head(i)))
guard(io.deq(i).bits.pos) := Bool(false) guard(deq(i).bits.pos) := Bool(false)
} }
when (enq =/= io.deq(i).fire()) { when (enq =/= deq(i).fire()) {
empty(i) := io.deq(i).fire() && last empty(i) := deq(i).fire() && last
} }
} }
} }