From dcb93835686dc771d1faca68fc5216daf99c8928 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 6 Oct 2016 15:34:13 -0700 Subject: [PATCH] PositionalMultiQueue: work around vcs Lint report Lint-[PCTIO-L] Ports coerced to inout rocket-chip/vsim/generated-src/unittest.UncoreUnitTestConfig.v, 127524 "io_deq_0_valid" Port "io_deq_0_valid" declared as output in module "PositionalMultiQueue_16" may need to be inout. Coercing to inout. --- .../scala/util/PositionalMultiQueue.scala | 23 +++++++++++-------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/src/main/scala/util/PositionalMultiQueue.scala b/src/main/scala/util/PositionalMultiQueue.scala index d47bbcba..cd87ebdc 100644 --- a/src/main/scala/util/PositionalMultiQueue.scala +++ b/src/main/scala/util/PositionalMultiQueue.scala @@ -47,6 +47,9 @@ class PositionalMultiQueue[T <: Data](params: PositionalMultiQueueParameters[T], guard(io.enq.bits.pos) := Bool(true) } + val deq = Wire(io.deq) + io.deq <> deq + val waySelect = UIntToOH(io.enq.bits.way, params.ways) for (i <- 0 until params.ways) { val enq = io.enq.fire() && waySelect(i) @@ -62,22 +65,22 @@ class PositionalMultiQueue[T <: Data](params: PositionalMultiQueueParameters[T], } if (combinational) { - io.deq(i).valid := !empty(i) || enq - io.deq(i).bits.pos := Mux(empty(i), io.enq.bits.pos, head(i)) - io.deq(i).bits.data := Mux(empty(i), io.enq.bits.data, data(head(i))) + deq(i).valid := !empty(i) || enq + deq(i).bits.pos := Mux(empty(i), io.enq.bits.pos, head(i)) + deq(i).bits.data := Mux(empty(i), io.enq.bits.data, data(head(i))) } else { - io.deq(i).valid := !empty(i) - io.deq(i).bits.pos := head(i) - io.deq(i).bits.data := data(head(i)) + deq(i).valid := !empty(i) + deq(i).bits.pos := head(i) + deq(i).bits.data := data(head(i)) } - when (io.deq(i).fire()) { + when (deq(i).fire()) { head(i) := Mux(last, io.enq.bits.pos, next(head(i))) - guard(io.deq(i).bits.pos) := Bool(false) + guard(deq(i).bits.pos) := Bool(false) } - when (enq =/= io.deq(i).fire()) { - empty(i) := io.deq(i).fire() && last + when (enq =/= deq(i).fire()) { + empty(i) := deq(i).fire() && last } } }