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coreplex: move TLBuffers for L2 and socBus

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This commit is contained in:
Wesley W. Terpstra 2017-01-20 22:23:36 -08:00
parent e8ce32a156
commit dcadd5a006
1 changed files with 2 additions and 3 deletions
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5
src/main/scala/coreplex/CoreplexNetwork.scala
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@ -34,9 +34,8 @@ trait CoreplexNetwork extends HasCoreplexParameters {
l1tol2.node)))
mmio :=
TLBuffer()(
TLWidthWidget(l1tol2_beatBytes)(
l1tol2.node))
l1tol2.node)
}
trait CoreplexNetworkBundle extends HasCoreplexParameters {
@ -99,7 +98,7 @@ trait BankedL2CoherenceManagersModule extends CoreplexNetworkModule {
trait HasL2MasterPort extends CoreplexNetwork {
val module: HasL2MasterPortModule
val l2in = TLInputNode()
l1tol2.node := l2in
l1tol2.node := TLBuffer()(l2in)
}
trait HasL2MasterPortBundle extends CoreplexNetworkBundle {