From dcadd5a006229db24cc91b9e8688b9e56e338844 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Fri, 20 Jan 2017 22:23:36 -0800
Subject: [PATCH] coreplex: move TLBuffers for L2 and socBus

---
 src/main/scala/coreplex/CoreplexNetwork.scala | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/coreplex/CoreplexNetwork.scala b/src/main/scala/coreplex/CoreplexNetwork.scala
index bce3a12e..aade8abf 100644
--- a/src/main/scala/coreplex/CoreplexNetwork.scala
+++ b/src/main/scala/coreplex/CoreplexNetwork.scala
@@ -34,9 +34,8 @@ trait CoreplexNetwork extends HasCoreplexParameters {
     l1tol2.node)))
 
   mmio :=
-    TLBuffer()(
     TLWidthWidget(l1tol2_beatBytes)(
-    l1tol2.node))
+    l1tol2.node)
 }
 
 trait CoreplexNetworkBundle extends HasCoreplexParameters {
@@ -99,7 +98,7 @@ trait BankedL2CoherenceManagersModule extends CoreplexNetworkModule {
 trait HasL2MasterPort extends CoreplexNetwork {
   val module: HasL2MasterPortModule
   val l2in = TLInputNode()
-  l1tol2.node := l2in
+  l1tol2.node := TLBuffer()(l2in)
 }
 
 trait HasL2MasterPortBundle extends CoreplexNetworkBundle {