riscv/rocket-chip
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Respect breakpoint privilege settings

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This commit is contained in:
Andrew Waterman 2016-06-09 12:41:52 -07:00
parent c85ea7b987
commit dca55a2b35
2 changed files with 7 additions and 3 deletions
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3
rocket/src/main/scala/breakpoint.scala
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@ -19,6 +19,7 @@ class BPControl extends Bundle {
class BreakpointUnit(implicit p: Parameters) extends CoreModule()(p) {
val io = new Bundle {
val status = new MStatus().asInput
val bpcontrol = Vec(p(NBreakpoints), new BPControl).asInput
val bpaddress = Vec(p(NBreakpoints), UInt(width = vaddrBits)).asInput
val pc = UInt(INPUT, vaddrBits)
@ -38,8 +39,10 @@ class BreakpointUnit(implicit p: Parameters) extends CoreModule()(p) {
mask = Cat(mask(i-1) && bpa(i-1), mask)
def matches(x: UInt) = (~x | mask) === (~bpa | mask)
when (Cat(bpc.m, bpc.h, bpc.s, bpc.u)(io.status.prv)) {
when (matches(io.pc) && bpc.x) { io.xcpt_if := true }
when (matches(io.ea) && bpc.r) { io.xcpt_ld := true }
when (matches(io.ea) && bpc.w) { io.xcpt_st := true }
}
}
}

1
rocket/src/main/scala/rocket.scala
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@ -227,6 +227,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc) || id_csr_en)
val bpu = Module(new BreakpointUnit)
bpu.io.status := csr.io.status
bpu.io.bpcontrol := csr.io.bpcontrol
bpu.io.bpaddress := csr.io.bpaddress
bpu.io.pc := id_pc