riscv/rocket-chip
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Respect breakpoint privilege settings

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This commit is contained in:
Andrew Waterman
2016-06-09 12:41:52 -07:00
parent c85ea7b987
commit dca55a2b35
2 changed files with 7 additions and 3 deletions
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rocket/src/main/scala/rocket.scala
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@ -227,6 +227,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc) || id_csr_en)
val bpu = Module(new BreakpointUnit)
bpu.io.status := csr.io.status
bpu.io.bpcontrol := csr.io.bpcontrol
bpu.io.bpaddress := csr.io.bpaddress
bpu.io.pc := id_pc