riscv/rocket-chip
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Work-around for current Scala compiler "structural type loses implicits".

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Running rocket-chip through the chisel3 gsdt branch which supports stricter connection checks and uses implicit definitions to deal with "old" direction overrides, exposed a possible bug in the Scala compiler.

    [error] .../src/main/scala/uncore/devices/Prci.scala:27: value asOutput is not a member of uncore.devices.PRCIInterrupts{val mtip: chisel3.core.Bool; val msip: chisel3.core.Bool}
    [error] possible cause: maybe a semicolon is missing before `value asOutput'?
    [error]   }.asOutput
    [error]     ^
    [error] one error found
    [error] (uncore/compile:compileIncremental) Compilation failed

This change isn't strictly required for current chisel3 code, but is being submitted in anticipation of an eventual merge of the gsdt branch prior to a compiler fix.
This commit is contained in:
Jim Lawson
2016-08-23 10:54:19 -07:00
committed by Andrew Waterman
parent fb50f7c9dd
commit dc9ae19936
1 changed files with 7 additions and 4 deletions
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11
src/main/scala/uncore/devices/Prci.scala
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@@ -22,10 +22,13 @@ class PRCIInterrupts extends Bundle {
class PRCITileIO(implicit p: Parameters) extends Bundle {
val reset = Bool(OUTPUT)
val id = UInt(OUTPUT, log2Up(p(NTiles)))
val interrupts = new PRCIInterrupts {
val mtip = Bool()
val msip = Bool()
}.asOutput
val interrupts = {
val result = new PRCIInterrupts {
val mtip = Bool()
val msip = Bool()
}
result.asOutput
}
override def cloneType: this.type = new PRCITileIO().asInstanceOf[this.type]
}