riscv/rocket-chip
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Specify width on s1_pc to avoid width inference problem

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This commit is contained in:
Andrew Waterman
2016-04-01 17:28:42 -07:00
parent 72f7f71eb5
commit dc662f28a0
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/frontend.scala
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@@ -37,7 +37,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
val icache = Module(new ICache) val icache = Module(new ICache)
val tlb = Module(new TLB) val tlb = Module(new TLB)
val s1_pc_ = Reg(UInt()) val s1_pc_ = Reg(UInt(width=vaddrBitsExtended))
val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline) val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline)
val s1_same_block = Reg(Bool()) val s1_same_block = Reg(Bool())
val s2_valid = Reg(init=Bool(true)) val s2_valid = Reg(init=Bool(true))