From dc662f28a00368c4e16705fc57162222b1f39d3c Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 1 Apr 2016 17:28:42 -0700 Subject: [PATCH] Specify width on s1_pc to avoid width inference problem --- rocket/src/main/scala/frontend.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/frontend.scala b/rocket/src/main/scala/frontend.scala index 0d3763c7..e0d7a1fb 100644 --- a/rocket/src/main/scala/frontend.scala +++ b/rocket/src/main/scala/frontend.scala @@ -37,7 +37,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa val icache = Module(new ICache) val tlb = Module(new TLB) - val s1_pc_ = Reg(UInt()) + val s1_pc_ = Reg(UInt(width=vaddrBitsExtended)) val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline) val s1_same_block = Reg(Bool()) val s2_valid = Reg(init=Bool(true))