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Silence Verilog compile warning from Cadence Incisive

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This commit is contained in:
Scott Johnson 2016-10-17 15:44:24 -07:00
parent c8fc05d154
commit dc4c375c7f
1 changed files with 1 additions and 1 deletions
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vsrc/TestDriver.v
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@ -22,7 +22,7 @@ module TestDriver;
int unsigned rand_value;
initial
begin
$value$plusargs("max-cycles=%d", max_cycles);
void'($value$plusargs("max-cycles=%d", max_cycles));
verbose = $test$plusargs("verbose");
// do not delete the line below.