axi4 tilelink2: include minAlignment and maxAddress in slaves
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@ -21,9 +21,10 @@ case class AXI4SlaveParameters(
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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val maxTransfer = max(supportsWrite.max, supportsRead.max)
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val maxAddress = address.map(_.max).max
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val minAlignment = address.map(_.alignment).min
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// The device had better not support a transfer larger than it's alignment
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address.foreach { case a => require (a.alignment >= maxTransfer) }
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require (minAlignment >= maxTransfer)
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}
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case class AXI4SlavePortParameters(
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@ -25,9 +25,7 @@ case class TLManagerParameters(
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customDTS: Option[String]= None)
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{
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address.foreach { a => require (a.finite) }
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address.combinations(2).foreach({ case Seq(x,y) =>
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require (!x.overlaps(y))
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})
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address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y)) }
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require (supportsPutFull.contains(supportsPutPartial))
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// Largest support transfer of all types
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@ -38,6 +36,7 @@ case class TLManagerParameters(
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supportsGet.max,
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supportsPutFull.max,
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supportsPutPartial.max).max
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val maxAddress = address.map(_.max).max
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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@ -53,9 +52,8 @@ case class TLManagerParameters(
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}
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// The device had better not support a transfer larger than it's alignment
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address.foreach({ case a =>
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require (a.alignment >= maxTransfer)
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})
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val minAlignment = address.map(_.alignment).min
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require (minAlignment >= maxTransfer)
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}
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case class TLManagerPortParameters(
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@ -77,7 +75,7 @@ case class TLManagerPortParameters(
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// Bounds on required sizes
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def endSinkId = managers.map(_.sinkId.end).max
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def maxAddress = managers.map(_.address.map(_.max).max).max
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def maxAddress = managers.map(_.maxAddress).max
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def maxTransfer = managers.map(_.maxTransfer).max
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// Operation sizes supported by all outward Managers
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