From dc26736f3256aee684e2dccf282a7a8005c7ce0e Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 11 Oct 2016 18:52:25 -0700 Subject: [PATCH] axi4 tilelink2: include minAlignment and maxAddress in slaves --- src/main/scala/uncore/axi4/Parameters.scala | 3 ++- src/main/scala/uncore/tilelink2/Parameters.scala | 12 +++++------- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/src/main/scala/uncore/axi4/Parameters.scala b/src/main/scala/uncore/axi4/Parameters.scala index dacc80ee..df430d76 100644 --- a/src/main/scala/uncore/axi4/Parameters.scala +++ b/src/main/scala/uncore/axi4/Parameters.scala @@ -21,9 +21,10 @@ case class AXI4SlaveParameters( val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected") val maxTransfer = max(supportsWrite.max, supportsRead.max) val maxAddress = address.map(_.max).max + val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than it's alignment - address.foreach { case a => require (a.alignment >= maxTransfer) } + require (minAlignment >= maxTransfer) } case class AXI4SlavePortParameters( diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index 27675f6e..097f7a22 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -25,9 +25,7 @@ case class TLManagerParameters( customDTS: Option[String]= None) { address.foreach { a => require (a.finite) } - address.combinations(2).foreach({ case Seq(x,y) => - require (!x.overlaps(y)) - }) + address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y)) } require (supportsPutFull.contains(supportsPutPartial)) // Largest support transfer of all types @@ -38,6 +36,7 @@ case class TLManagerParameters( supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max + val maxAddress = address.map(_.max).max val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected") @@ -53,9 +52,8 @@ case class TLManagerParameters( } // The device had better not support a transfer larger than it's alignment - address.foreach({ case a => - require (a.alignment >= maxTransfer) - }) + val minAlignment = address.map(_.alignment).min + require (minAlignment >= maxTransfer) } case class TLManagerPortParameters( @@ -77,7 +75,7 @@ case class TLManagerPortParameters( // Bounds on required sizes def endSinkId = managers.map(_.sinkId.end).max - def maxAddress = managers.map(_.address.map(_.max).max).max + def maxAddress = managers.map(_.maxAddress).max def maxTransfer = managers.map(_.maxTransfer).max // Operation sizes supported by all outward Managers