riscv/rocket-chip
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axi4 tilelink2: include minAlignment and maxAddress in slaves

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This commit is contained in:
Wesley W. Terpstra 2016-10-11 18:52:25 -07:00
parent 538437384a
commit dc26736f32
2 changed files with 7 additions and 8 deletions
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3
src/main/scala/uncore/axi4/Parameters.scala
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@ -21,9 +21,10 @@ case class AXI4SlaveParameters(
val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected") val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
val maxTransfer = max(supportsWrite.max, supportsRead.max) val maxTransfer = max(supportsWrite.max, supportsRead.max)
val maxAddress = address.map(_.max).max val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than it's alignment // The device had better not support a transfer larger than it's alignment
address.foreach { case a => require (a.alignment >= maxTransfer) } require (minAlignment >= maxTransfer)
} }
case class AXI4SlavePortParameters( case class AXI4SlavePortParameters(

12
src/main/scala/uncore/tilelink2/Parameters.scala
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@ -25,9 +25,7 @@ case class TLManagerParameters(
customDTS: Option[String]= None) customDTS: Option[String]= None)
{ {
address.foreach { a => require (a.finite) } address.foreach { a => require (a.finite) }
address.combinations(2).foreach({ case Seq(x,y) => address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y)) }
require (!x.overlaps(y))
})
require (supportsPutFull.contains(supportsPutPartial)) require (supportsPutFull.contains(supportsPutPartial))
// Largest support transfer of all types // Largest support transfer of all types
@ -38,6 +36,7 @@ case class TLManagerParameters(
supportsGet.max, supportsGet.max,
supportsPutFull.max, supportsPutFull.max,
supportsPutPartial.max).max supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected") val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
@ -53,9 +52,8 @@ case class TLManagerParameters(
} }
// The device had better not support a transfer larger than it's alignment // The device had better not support a transfer larger than it's alignment
address.foreach({ case a => val minAlignment = address.map(_.alignment).min
require (a.alignment >= maxTransfer) require (minAlignment >= maxTransfer)
})
} }
case class TLManagerPortParameters( case class TLManagerPortParameters(
@ -77,7 +75,7 @@ case class TLManagerPortParameters(
// Bounds on required sizes // Bounds on required sizes
def endSinkId = managers.map(_.sinkId.end).max def endSinkId = managers.map(_.sinkId.end).max
def maxAddress = managers.map(_.address.map(_.max).max).max def maxAddress = managers.map(_.maxAddress).max
def maxTransfer = managers.map(_.maxTransfer).max def maxTransfer = managers.map(_.maxTransfer).max
// Operation sizes supported by all outward Managers // Operation sizes supported by all outward Managers