riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2: defer bundle construction until after Module base class instantiated

Browse Source
This commit is contained in:
Wesley W. Terpstra
2016-08-29 11:08:37 -07:00
parent 18e149098a
commit dc1164a996
1 changed files with 3 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
uncore/src/main/scala/tilelink2/RegisterRouter.scala
View File

@@ -102,16 +102,17 @@ abstract class TLRegFactory(address: AddressSet, beatBytes: Int) extends TLFacto
class TLRegBundle[P](val params: P, val tl_in: Vec[TLBundle]) extends Bundle
class TLRegModule[P, B <: Bundle](val params: P, val io: B, factory: TLRegFactory)
class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, factory: TLRegFactory)
extends TLModule(factory) with HasRegMap
{
val io = bundleBuilder
def regmap(mapping: RegField.Map*) = factory.node.regmap(mapping:_*)
}
class TLRegisterRouter[B <: Bundle, M <: TLModule]
(address: Option[BigInt] = None, size: BigInt = 4096, beatBytes: Int = 4)
(bundleBuilder: Vec[TLBundle] => B)
(moduleBuilder: (B, TLRegFactory) => M)
(moduleBuilder: (=> B, TLRegFactory) => M)
extends TLRegFactory(AddressSet(size-1, address), beatBytes)
{
require (size % 4096 == 0) // devices should be 4K aligned