From dc1164a99669f95a80195d0669acc9d99565e005 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 29 Aug 2016 11:08:37 -0700 Subject: [PATCH] tilelink2: defer bundle construction until after Module base class instantiated --- uncore/src/main/scala/tilelink2/RegisterRouter.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/uncore/src/main/scala/tilelink2/RegisterRouter.scala b/uncore/src/main/scala/tilelink2/RegisterRouter.scala index cda3426e..8d6b764a 100644 --- a/uncore/src/main/scala/tilelink2/RegisterRouter.scala +++ b/uncore/src/main/scala/tilelink2/RegisterRouter.scala @@ -102,16 +102,17 @@ abstract class TLRegFactory(address: AddressSet, beatBytes: Int) extends TLFacto class TLRegBundle[P](val params: P, val tl_in: Vec[TLBundle]) extends Bundle -class TLRegModule[P, B <: Bundle](val params: P, val io: B, factory: TLRegFactory) +class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, factory: TLRegFactory) extends TLModule(factory) with HasRegMap { + val io = bundleBuilder def regmap(mapping: RegField.Map*) = factory.node.regmap(mapping:_*) } class TLRegisterRouter[B <: Bundle, M <: TLModule] (address: Option[BigInt] = None, size: BigInt = 4096, beatBytes: Int = 4) (bundleBuilder: Vec[TLBundle] => B) - (moduleBuilder: (B, TLRegFactory) => M) + (moduleBuilder: (=> B, TLRegFactory) => M) extends TLRegFactory(AddressSet(size-1, address), beatBytes) { require (size % 4096 == 0) // devices should be 4K aligned