riscv/rocket-chip
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This commit is contained in:
Henry Cook 2017-03-09 18:56:54 -08:00 committed by Andrew Waterman
parent 380c10f7bd
commit dbc8f4b30b
4 changed files with 9 additions and 5 deletions
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4
src/main/scala/rocket/DCache.scala
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@ -505,6 +505,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
} }
// performance events // performance events
io.cpu.acquire := edge.last(tl_out.a) io.cpu.acquire := edge.done(tl_out.a)
io.cpu.release := edge.last(tl_out.c) io.cpu.release := edge.done(tl_out.c)
} }

2
src/main/scala/rocket/Frontend.scala
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@ -155,7 +155,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
io.cpu.resp.bits.btb.bits := s2_btb_resp_bits io.cpu.resp.bits.btb.bits := s2_btb_resp_bits
// performance events // performance events
io.cpu.acquire := edge.last(icache.io.mem(0).a) io.cpu.acquire := edge.done(icache.io.mem(0).a)
} }
/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */ /** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */

4
src/main/scala/rocket/NBDcache.scala
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@ -975,6 +975,6 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
io.cpu.replay_next := (s1_replay && s1_read) || mshrs.io.replay_next io.cpu.replay_next := (s1_replay && s1_read) || mshrs.io.replay_next
// performance events // performance events
io.cpu.acquire := edge.last(tl_out.a) io.cpu.acquire := edge.done(tl_out.a)
io.cpu.release := edge.last(tl_out.c) io.cpu.release := edge.done(tl_out.c)
} }

4
src/main/scala/uncore/tilelink2/Edges.scala
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@ -224,6 +224,10 @@ class TLEdge(
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire()) def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire())
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire())
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire) val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3) (r._1, r._2, r._3)