riscv/rocket-chip
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last => done

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This commit is contained in:
Henry Cook
2017-03-09 18:56:54 -08:00
committed by Andrew Waterman
parent 380c10f7bd
commit dbc8f4b30b
4 changed files with 9 additions and 5 deletions
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src/main/scala/rocket/Frontend.scala
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@ -155,7 +155,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
io.cpu.resp.bits.btb.bits := s2_btb_resp_bits
// performance events
io.cpu.acquire := edge.last(icache.io.mem(0).a)
io.cpu.acquire := edge.done(icache.io.mem(0).a)
}
/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */