Generate and use SCR address header files

This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).

Makefrag

@@ -51,6 +51,7 @@ $(sim_dir)/libdramsim.a: $(DRAMSIM_OBJS)
 
 params_file = $(generated_dir)/$(MODEL).$(CONFIG).prm
 consts_header = $(generated_dir)/consts.$(CONFIG).h
+scr_header = $(generated_dir)/$(MODEL).$(CONFIG).scr_map.h
 $(consts_header): $(params_file)
 	echo "#ifndef __CONST_H__" > $@
 	echo "#define __CONST_H__" >> $@

csrc/htif_emulator.h

@@ -16,7 +16,7 @@ class htif_emulator_t : public htif_pthread_t
 
   void set_clock_divisor(int divisor, int hold_cycles)
   {
-    write_cr(-1, 63, divisor | hold_cycles << 16);
+    write_cr(-1, UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR, divisor | hold_cycles << 16);
   }
 
   void start()

emulator/Makefile

@@ -36,7 +36,7 @@ $(generated_dir_debug)/%.o: $(generated_dir_debug)/%.cpp $(generated_dir_debug)/
 	$(CXX) $(CXXFLAGS) -I$(generated_dir_debug) -c -o $@ $<
 
 $(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header) $(consts_header)
-	$(CXX) $(CXXFLAGS) -include $(model_header) -include $(consts_header) -I$(generated_dir) -c -o $@ $<
+	$(CXX) $(CXXFLAGS) -include $(scr_header) -include $(model_header) -include $(consts_header) -I$(generated_dir) -c -o $@ $<
 
 $(addsuffix .debug.o,$(CXXSRCS)): %.debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header_debug) $(consts_header_debug)
 	$(CXX) $(CXXFLAGS) -include $(model_header_debug) -include $(consts_header_debug) -I$(generated_dir_debug) -c -o $@ $<

fsim/Makefrag

@@ -41,6 +41,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	-CC "-std=c++11" \
 	-CC "-Wl,-rpath,$(RISCV)/lib" \
 	-CC "-include $(consts_header)" \
+	-CC "-include $(scr_header)" \
 	-e vcs_main \
 	$(RISCV)/lib/libfesvr.so \
 	$(sim_dir)/libdramsim.a \

src/main/scala/RocketChip.scala

@@ -160,7 +160,7 @@ class Uncore(implicit val p: Parameters) extends Module
   }
 
   // Arbitrate SCR access between MMIO and HTIF
-  val scrFile = Module(new SCRFile)
+  val scrFile = Module(new SCRFile("UNCORE_SCR"))
   val scrArb = Module(new SmiArbiter(2, scrDataBits, scrAddrBits))
   scrArb.io.in(0) <> htif.io.scr
   scrArb.io.in(1) <> outmemsys.io.scr

src/main/scala/Testing.scala

@@ -5,6 +5,7 @@ package rocketchip
 import Chisel._
 import scala.collection.mutable.LinkedHashSet
 import cde.{Parameters, ParameterDump, Config}
+import uncore.AllSCRFiles
 
 abstract class RocketTestSuite {
   val dir: String
@@ -171,4 +172,7 @@ object TestGenerator extends App with FileSystemUtilities {
   val w = createOutputFile(configClassName + ".cst")
   w.write(world.getConstraints)
   w.close
+  val scr_map_hdr = createOutputFile(topModuleName + "." + configClassName + ".scr_map.h")
+  AllSCRFiles.foreach{ map => scr_map_hdr.write(map.as_c_header) }
+  scr_map_hdr.close
 }

src/main/scala/Vlsi.scala

@@ -76,6 +76,7 @@ object VLSIUtils {
     hio.io.set_divisor.valid := scr.wen && (scr.waddr === UInt(63))
     hio.io.set_divisor.bits := scr.wdata
     scr.rdata(63) := hio.io.divisor
+    scr.allocate(63, "HTIF_IO_CLOCK_DIVISOR")
 
     hio.io.out_fast.valid := htif.out.valid || child.req.valid
     hio.io.out_fast.bits := Cat(htif.out.valid, Mux(htif.out.valid, htif.out.bits, child.req.bits))

uncore

@@ -1 +1 @@
-Subproject commit 9af7cf79a45ddf010a913cea2ad9bfa254174cbe
+Subproject commit 6e4d5602376404836dab6ec6d806437e6886c049

vsim/Makefrag

@@ -40,6 +40,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	-CC "-std=c++11" \
 	-CC "-Wl,-rpath,$(RISCV)/lib" \
 	-CC "-include $(consts_header)" \
+	-CC "-include $(scr_header)" \
 	-e vcs_main \
 	$(RISCV)/lib/libfesvr.so \
 	$(sim_dir)/libdramsim.a \