From db9de94588dfe1ff7f7d0c19f12eba1d0aa5a209 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Wed, 17 Feb 2016 15:23:18 -0800 Subject: [PATCH] Generate and use SCR address header files This uses the new SCRFile changes to generate a header file containing a list of all the SCRs in a core to remove the magic constant "63" (the HTIF clock divider control register) and replace it with a generated number (which is still 63). --- Makefrag | 1 + csrc/htif_emulator.h | 2 +- emulator/Makefile | 2 +- fsim/Makefrag | 1 + src/main/scala/RocketChip.scala | 2 +- src/main/scala/Testing.scala | 4 ++++ src/main/scala/Vlsi.scala | 1 + uncore | 2 +- vsim/Makefrag | 1 + 9 files changed, 12 insertions(+), 4 deletions(-) diff --git a/Makefrag b/Makefrag index 6d8eeb10..45852edf 100644 --- a/Makefrag +++ b/Makefrag @@ -51,6 +51,7 @@ $(sim_dir)/libdramsim.a: $(DRAMSIM_OBJS) params_file = $(generated_dir)/$(MODEL).$(CONFIG).prm consts_header = $(generated_dir)/consts.$(CONFIG).h +scr_header = $(generated_dir)/$(MODEL).$(CONFIG).scr_map.h $(consts_header): $(params_file) echo "#ifndef __CONST_H__" > $@ echo "#define __CONST_H__" >> $@ diff --git a/csrc/htif_emulator.h b/csrc/htif_emulator.h index de9b416f..7c329962 100644 --- a/csrc/htif_emulator.h +++ b/csrc/htif_emulator.h @@ -16,7 +16,7 @@ class htif_emulator_t : public htif_pthread_t void set_clock_divisor(int divisor, int hold_cycles) { - write_cr(-1, 63, divisor | hold_cycles << 16); + write_cr(-1, UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR, divisor | hold_cycles << 16); } void start() diff --git a/emulator/Makefile b/emulator/Makefile index 9aee51fd..e54124ad 100644 --- a/emulator/Makefile +++ b/emulator/Makefile @@ -36,7 +36,7 @@ $(generated_dir_debug)/%.o: $(generated_dir_debug)/%.cpp $(generated_dir_debug)/ $(CXX) $(CXXFLAGS) -I$(generated_dir_debug) -c -o $@ $< $(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header) $(consts_header) - $(CXX) $(CXXFLAGS) -include $(model_header) -include $(consts_header) -I$(generated_dir) -c -o $@ $< + $(CXX) $(CXXFLAGS) -include $(scr_header) -include $(model_header) -include $(consts_header) -I$(generated_dir) -c -o $@ $< $(addsuffix .debug.o,$(CXXSRCS)): %.debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header_debug) $(consts_header_debug) $(CXX) $(CXXFLAGS) -include $(model_header_debug) -include $(consts_header_debug) -I$(generated_dir_debug) -c -o $@ $< diff --git a/fsim/Makefrag b/fsim/Makefrag index 916814c8..d8faddea 100644 --- a/fsim/Makefrag +++ b/fsim/Makefrag @@ -41,6 +41,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1 -CC "-std=c++11" \ -CC "-Wl,-rpath,$(RISCV)/lib" \ -CC "-include $(consts_header)" \ + -CC "-include $(scr_header)" \ -e vcs_main \ $(RISCV)/lib/libfesvr.so \ $(sim_dir)/libdramsim.a \ diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 3e1efeaf..9db0d6d8 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -160,7 +160,7 @@ class Uncore(implicit val p: Parameters) extends Module } // Arbitrate SCR access between MMIO and HTIF - val scrFile = Module(new SCRFile) + val scrFile = Module(new SCRFile("UNCORE_SCR")) val scrArb = Module(new SmiArbiter(2, scrDataBits, scrAddrBits)) scrArb.io.in(0) <> htif.io.scr scrArb.io.in(1) <> outmemsys.io.scr diff --git a/src/main/scala/Testing.scala b/src/main/scala/Testing.scala index 2540d83b..a3a58132 100644 --- a/src/main/scala/Testing.scala +++ b/src/main/scala/Testing.scala @@ -5,6 +5,7 @@ package rocketchip import Chisel._ import scala.collection.mutable.LinkedHashSet import cde.{Parameters, ParameterDump, Config} +import uncore.AllSCRFiles abstract class RocketTestSuite { val dir: String @@ -171,4 +172,7 @@ object TestGenerator extends App with FileSystemUtilities { val w = createOutputFile(configClassName + ".cst") w.write(world.getConstraints) w.close + val scr_map_hdr = createOutputFile(topModuleName + "." + configClassName + ".scr_map.h") + AllSCRFiles.foreach{ map => scr_map_hdr.write(map.as_c_header) } + scr_map_hdr.close } diff --git a/src/main/scala/Vlsi.scala b/src/main/scala/Vlsi.scala index bb4f6f5c..7492e79c 100644 --- a/src/main/scala/Vlsi.scala +++ b/src/main/scala/Vlsi.scala @@ -76,6 +76,7 @@ object VLSIUtils { hio.io.set_divisor.valid := scr.wen && (scr.waddr === UInt(63)) hio.io.set_divisor.bits := scr.wdata scr.rdata(63) := hio.io.divisor + scr.allocate(63, "HTIF_IO_CLOCK_DIVISOR") hio.io.out_fast.valid := htif.out.valid || child.req.valid hio.io.out_fast.bits := Cat(htif.out.valid, Mux(htif.out.valid, htif.out.bits, child.req.bits)) diff --git a/uncore b/uncore index 9af7cf79..6e4d5602 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 9af7cf79a45ddf010a913cea2ad9bfa254174cbe +Subproject commit 6e4d5602376404836dab6ec6d806437e6886c049 diff --git a/vsim/Makefrag b/vsim/Makefrag index 321c2e93..683bd131 100644 --- a/vsim/Makefrag +++ b/vsim/Makefrag @@ -40,6 +40,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1 -CC "-std=c++11" \ -CC "-Wl,-rpath,$(RISCV)/lib" \ -CC "-include $(consts_header)" \ + -CC "-include $(scr_header)" \ -e vcs_main \ $(RISCV)/lib/libfesvr.so \ $(sim_dir)/libdramsim.a \