Generate and use SCR address header files
This uses the new SCRFile changes to generate a header file containing a list of all the SCRs in a core to remove the magic constant "63" (the HTIF clock divider control register) and replace it with a generated number (which is still 63).
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parent
8687ce5ebd
commit
db9de94588
1
Makefrag
1
Makefrag
@ -51,6 +51,7 @@ $(sim_dir)/libdramsim.a: $(DRAMSIM_OBJS)
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params_file = $(generated_dir)/$(MODEL).$(CONFIG).prm
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params_file = $(generated_dir)/$(MODEL).$(CONFIG).prm
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consts_header = $(generated_dir)/consts.$(CONFIG).h
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consts_header = $(generated_dir)/consts.$(CONFIG).h
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scr_header = $(generated_dir)/$(MODEL).$(CONFIG).scr_map.h
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$(consts_header): $(params_file)
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$(consts_header): $(params_file)
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echo "#ifndef __CONST_H__" > $@
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echo "#ifndef __CONST_H__" > $@
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echo "#define __CONST_H__" >> $@
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echo "#define __CONST_H__" >> $@
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@ -16,7 +16,7 @@ class htif_emulator_t : public htif_pthread_t
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void set_clock_divisor(int divisor, int hold_cycles)
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void set_clock_divisor(int divisor, int hold_cycles)
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{
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{
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write_cr(-1, 63, divisor | hold_cycles << 16);
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write_cr(-1, UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR, divisor | hold_cycles << 16);
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}
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}
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void start()
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void start()
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@ -36,7 +36,7 @@ $(generated_dir_debug)/%.o: $(generated_dir_debug)/%.cpp $(generated_dir_debug)/
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$(CXX) $(CXXFLAGS) -I$(generated_dir_debug) -c -o $@ $<
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$(CXX) $(CXXFLAGS) -I$(generated_dir_debug) -c -o $@ $<
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$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header) $(consts_header)
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$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header) $(consts_header)
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$(CXX) $(CXXFLAGS) -include $(model_header) -include $(consts_header) -I$(generated_dir) -c -o $@ $<
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$(CXX) $(CXXFLAGS) -include $(scr_header) -include $(model_header) -include $(consts_header) -I$(generated_dir) -c -o $@ $<
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$(addsuffix .debug.o,$(CXXSRCS)): %.debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header_debug) $(consts_header_debug)
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$(addsuffix .debug.o,$(CXXSRCS)): %.debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header_debug) $(consts_header_debug)
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$(CXX) $(CXXFLAGS) -include $(model_header_debug) -include $(consts_header_debug) -I$(generated_dir_debug) -c -o $@ $<
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$(CXX) $(CXXFLAGS) -include $(model_header_debug) -include $(consts_header_debug) -I$(generated_dir_debug) -c -o $@ $<
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@ -41,6 +41,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
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-CC "-std=c++11" \
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-CC "-std=c++11" \
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-CC "-Wl,-rpath,$(RISCV)/lib" \
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-CC "-Wl,-rpath,$(RISCV)/lib" \
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-CC "-include $(consts_header)" \
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-CC "-include $(consts_header)" \
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-CC "-include $(scr_header)" \
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-e vcs_main \
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-e vcs_main \
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$(RISCV)/lib/libfesvr.so \
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$(RISCV)/lib/libfesvr.so \
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$(sim_dir)/libdramsim.a \
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$(sim_dir)/libdramsim.a \
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@ -160,7 +160,7 @@ class Uncore(implicit val p: Parameters) extends Module
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}
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}
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// Arbitrate SCR access between MMIO and HTIF
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// Arbitrate SCR access between MMIO and HTIF
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val scrFile = Module(new SCRFile)
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val scrFile = Module(new SCRFile("UNCORE_SCR"))
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val scrArb = Module(new SmiArbiter(2, scrDataBits, scrAddrBits))
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val scrArb = Module(new SmiArbiter(2, scrDataBits, scrAddrBits))
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scrArb.io.in(0) <> htif.io.scr
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scrArb.io.in(0) <> htif.io.scr
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scrArb.io.in(1) <> outmemsys.io.scr
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scrArb.io.in(1) <> outmemsys.io.scr
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@ -5,6 +5,7 @@ package rocketchip
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import Chisel._
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import Chisel._
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import scala.collection.mutable.LinkedHashSet
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import scala.collection.mutable.LinkedHashSet
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import cde.{Parameters, ParameterDump, Config}
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import cde.{Parameters, ParameterDump, Config}
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import uncore.AllSCRFiles
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abstract class RocketTestSuite {
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abstract class RocketTestSuite {
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val dir: String
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val dir: String
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@ -171,4 +172,7 @@ object TestGenerator extends App with FileSystemUtilities {
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val w = createOutputFile(configClassName + ".cst")
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val w = createOutputFile(configClassName + ".cst")
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w.write(world.getConstraints)
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w.write(world.getConstraints)
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w.close
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w.close
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val scr_map_hdr = createOutputFile(topModuleName + "." + configClassName + ".scr_map.h")
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AllSCRFiles.foreach{ map => scr_map_hdr.write(map.as_c_header) }
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scr_map_hdr.close
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}
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}
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@ -76,6 +76,7 @@ object VLSIUtils {
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hio.io.set_divisor.valid := scr.wen && (scr.waddr === UInt(63))
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hio.io.set_divisor.valid := scr.wen && (scr.waddr === UInt(63))
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hio.io.set_divisor.bits := scr.wdata
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hio.io.set_divisor.bits := scr.wdata
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scr.rdata(63) := hio.io.divisor
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scr.rdata(63) := hio.io.divisor
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scr.allocate(63, "HTIF_IO_CLOCK_DIVISOR")
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hio.io.out_fast.valid := htif.out.valid || child.req.valid
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hio.io.out_fast.valid := htif.out.valid || child.req.valid
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hio.io.out_fast.bits := Cat(htif.out.valid, Mux(htif.out.valid, htif.out.bits, child.req.bits))
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hio.io.out_fast.bits := Cat(htif.out.valid, Mux(htif.out.valid, htif.out.bits, child.req.bits))
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2
uncore
2
uncore
@ -1 +1 @@
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Subproject commit 9af7cf79a45ddf010a913cea2ad9bfa254174cbe
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Subproject commit 6e4d5602376404836dab6ec6d806437e6886c049
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@ -40,6 +40,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
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-CC "-std=c++11" \
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-CC "-std=c++11" \
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-CC "-Wl,-rpath,$(RISCV)/lib" \
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-CC "-Wl,-rpath,$(RISCV)/lib" \
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-CC "-include $(consts_header)" \
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-CC "-include $(consts_header)" \
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-CC "-include $(scr_header)" \
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-e vcs_main \
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-e vcs_main \
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$(RISCV)/lib/libfesvr.so \
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$(RISCV)/lib/libfesvr.so \
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$(sim_dir)/libdramsim.a \
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$(sim_dir)/libdramsim.a \
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