Generate and use SCR address header files

This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).

src/main/scala/RocketChip.scala

@@ -160,7 +160,7 @@ class Uncore(implicit val p: Parameters) extends Module
   }
 
   // Arbitrate SCR access between MMIO and HTIF
-  val scrFile = Module(new SCRFile)
+  val scrFile = Module(new SCRFile("UNCORE_SCR"))
   val scrArb = Module(new SmiArbiter(2, scrDataBits, scrAddrBits))
   scrArb.io.in(0) <> htif.io.scr
   scrArb.io.in(1) <> outmemsys.io.scr