Generate and use SCR address header files

This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).

src/main/scala/RocketChip.scala

@@ -160,7 +160,7 @@ class Uncore(implicit val p: Parameters) extends Module
   }
 
   // Arbitrate SCR access between MMIO and HTIF
-  val scrFile = Module(new SCRFile)
+  val scrFile = Module(new SCRFile("UNCORE_SCR"))
   val scrArb = Module(new SmiArbiter(2, scrDataBits, scrAddrBits))
   scrArb.io.in(0) <> htif.io.scr
   scrArb.io.in(1) <> outmemsys.io.scr

src/main/scala/Testing.scala

@@ -5,6 +5,7 @@ package rocketchip
 import Chisel._
 import scala.collection.mutable.LinkedHashSet
 import cde.{Parameters, ParameterDump, Config}
+import uncore.AllSCRFiles
 
 abstract class RocketTestSuite {
   val dir: String
@@ -171,4 +172,7 @@ object TestGenerator extends App with FileSystemUtilities {
   val w = createOutputFile(configClassName + ".cst")
   w.write(world.getConstraints)
   w.close
+  val scr_map_hdr = createOutputFile(topModuleName + "." + configClassName + ".scr_map.h")
+  AllSCRFiles.foreach{ map => scr_map_hdr.write(map.as_c_header) }
+  scr_map_hdr.close
 }

src/main/scala/Vlsi.scala

@@ -76,6 +76,7 @@ object VLSIUtils {
     hio.io.set_divisor.valid := scr.wen && (scr.waddr === UInt(63))
     hio.io.set_divisor.bits := scr.wdata
     scr.rdata(63) := hio.io.divisor
+    scr.allocate(63, "HTIF_IO_CLOCK_DIVISOR")
 
     hio.io.out_fast.valid := htif.out.valid || child.req.valid
     hio.io.out_fast.bits := Cat(htif.out.valid, Mux(htif.out.valid, htif.out.bits, child.req.bits))