riscv/rocket-chip
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hwacha

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This commit is contained in:
Huy Vo 2012-07-27 18:12:23 -07:00
parent 32a16d183f
commit db91c4cf6c
2 changed files with 2 additions and 6 deletions
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5
rocket/src/main/scala/consts.scala
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@ -5,16 +5,13 @@ import scala.math._
object Constants object Constants
{ {
val NTILES = 2 val NTILES = 1
val HAVE_RVC = false val HAVE_RVC = false
val HAVE_FPU = true val HAVE_FPU = true
val HAVE_VEC = true val HAVE_VEC = true
val MAX_THREADS = val MAX_THREADS =
if(hwacha.Constants.HAVE_PVFB)
hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK
else
256
val HTIF_WIDTH = 16 val HTIF_WIDTH = 16
val MEM_BACKUP_WIDTH = HTIF_WIDTH val MEM_BACKUP_WIDTH = HTIF_WIDTH

3
rocket/src/main/scala/dpath_vec.scala
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@ -105,8 +105,7 @@ class rocketDpathVec extends Component
UFix(52,7) -> UFix(5,9) UFix(52,7) -> UFix(5,9)
)) ))
val uts_per_bank = Mux(nreg_mod_bank > UFix(MAX_THREADS,9), UFix(MAX_THREADS, 9), nreg_mod_bank) val uts_per_bank = Mux(Bool(hwacha.Constants.HAVE_PVFB) & nreg_mod_bank > UFix(MAX_THREADS,9), UFix(MAX_THREADS, 9), nreg_mod_bank)
val reg_hwvl = Reg(resetVal = UFix(32, 12)) val reg_hwvl = Reg(resetVal = UFix(32, 12))
val reg_appvl0 = Reg(resetVal = Bool(true)) val reg_appvl0 = Reg(resetVal = Bool(true))