diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala
index 54786a23..78f979d8 100644
--- a/rocket/src/main/scala/consts.scala
+++ b/rocket/src/main/scala/consts.scala
@@ -5,16 +5,13 @@ import scala.math._
 
 object Constants
 {
-  val NTILES = 2
+  val NTILES = 1
   val HAVE_RVC = false
   val HAVE_FPU = true
   val HAVE_VEC = true
 
   val MAX_THREADS = 
-    if(hwacha.Constants.HAVE_PVFB)
       hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK
-    else
-      256
 
   val HTIF_WIDTH = 16
   val MEM_BACKUP_WIDTH = HTIF_WIDTH
diff --git a/rocket/src/main/scala/dpath_vec.scala b/rocket/src/main/scala/dpath_vec.scala
index 6f5f228f..8a4faabb 100644
--- a/rocket/src/main/scala/dpath_vec.scala
+++ b/rocket/src/main/scala/dpath_vec.scala
@@ -105,8 +105,7 @@ class rocketDpathVec extends Component
       UFix(52,7) -> UFix(5,9)
     ))
 
-  val uts_per_bank = Mux(nreg_mod_bank > UFix(MAX_THREADS,9), UFix(MAX_THREADS, 9), nreg_mod_bank)
-
+  val uts_per_bank = Mux(Bool(hwacha.Constants.HAVE_PVFB) & nreg_mod_bank > UFix(MAX_THREADS,9), UFix(MAX_THREADS, 9), nreg_mod_bank)
 
   val reg_hwvl = Reg(resetVal = UFix(32, 12))
   val reg_appvl0 = Reg(resetVal = Bool(true))