riscv/rocket-chip
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made eret instruction take an illegal inst exception when ET is set

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This commit is contained in:
Rimas Avizienis
2011-11-14 14:35:10 -08:00
parent cd6e463320
commit db87924fbf
3 changed files with 12 additions and 8 deletions
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7
rocket/src/main/scala/consts.scala
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@ -155,8 +155,8 @@ object Constants
val PCR_COMPARE = UFix( 5, 5);
val PCR_CAUSE = UFix( 6, 5);
val PCR_PTBR = UFix( 7, 5);
val PCR_SENDIPI = UFix( 8, 5);
val PCR_CLEARIPI = UFix( 9, 5);
val PCR_SEND_IPI = UFix( 8, 5);
val PCR_CLR_IPI = UFix( 9, 5);
val PCR_COREID = UFix(10, 5);
val PCR_K0 = UFix(12, 5);
val PCR_K1 = UFix(13, 5);
@ -169,6 +169,7 @@ object Constants
val SR_ET = 0; // enable traps
val SR_EF = 1; // enable floating point
val SR_EV = 2; // enable vector unit
val SR_EC = 3; // enable compressed instruction encoding
val SR_PS = 4; // mode stack bit
val SR_S = 5; // user/supervisor mode
val SR_UX = 6; // 64 bit user mode
@ -176,7 +177,6 @@ object Constants
val SR_VM = 16; // VM enable
val COREID = 0;
val NUMCORES = 1;
val PADDR_BITS = 40;
val VADDR_BITS = 43;
val PGIDX_BITS = 13;
@ -195,6 +195,7 @@ object Constants
val START_ADDR = 0x2000;
val HAVE_RVC = Bool(false);
val HAVE_FPU = Bool(false);
val HAVE_VEC = Bool(false);
}